HD6417041AVF16V Renesas Electronics America, HD6417041AVF16V Datasheet - Page 218

• Manufacturer Part Number: HD6417041AVF16V
• Description: IC SUPERH MCU ROMLESS 144QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7040r

Specifications of HD6417041AVF16V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 28.7MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 6 Instruction Descriptions
6.1.34
Format
MOV
MOV.W @(disp,
MOV.L @(disp,
Description: Stores immediate data, which has been sign-extended to a longword, into general
register Rn.
If the data is a word or longword, table data stored in the address specified by PC + displacement
is accessed. If the data is a word, the 8-bit displacement is zero-extended and doubled.
Consequently, the relative interval from the table can be up to PC + 510 bytes. The PC points to
the starting address of the second instruction after this MOV instruction. If the data is a longword,
the 8-bit displacement is zero-extended and quadrupled. Consequently, the relative interval from
the table can be up to PC + 1020 bytes. The PC points to the starting address of the second
instruction after this MOV instruction, but the lowest two bits of the PC are corrected to B'00.
Note: The optimum table assignment is at the rear end of the module or one instruction after the
Operation:
Rev. 5.00 Jun 30, 2004 page 202 of 512
REJ09B0171-0500O
MOVI(long i,long n)
{
}
if ((i&0x80)==0) R[n]=(0x000000FF & (long)i);
else R[n]=(0xFFFFFF00 | (long)i);
PC+=2;
#imm,Rn
PC),Rn
PC),Rn
unconditional branch instruction. If the optimum assignment is impossible for the reason
of no unconditional branch instruction in the 510 byte/1020 byte or some other reason,
means to jump past the table by the BRA instruction are required. By assigning this
instruction immediately after the delayed branch instruction, the PC becomes the "first
address + 2".
MOV (Move Immediate Data): Data Transfer Instruction
Abstract
imm
extension
(disp
extension
(disp
2 + PC)
4 + PC)
sign
Rn
Rn
/* MOV #imm,Rn */
sign
Rn
Code
1110nnnniiiiiiii
1001nnnndddddddd
1101nnnndddddddd
Cycle
1
1
1
T
Bit
—
—
—
SH-1
Instructions
Applicable
SH-2
SH-
DSP