HD6417041AVF16V Renesas Electronics America, HD6417041AVF16V Datasheet - Page 497
HD6417041AVF16V
Manufacturer Part Number
HD6417041AVF16V
Description
IC SUPERH MCU ROMLESS 144QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7040r
Specifications of HD6417041AVF16V
Core Processor
SH-2
Core Size
32-Bit
Speed
28.7MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417041AVF16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Double-Length Multiplication Instructions (SH-2 CPU, SH-DSP): Include the following
instruction types:
The pipeline has nine stages: IF, ID, EX, MA, MA, mm, mm, mm, and mm (figure 7.72). The
second MA accesses the multiplier. The mm indicates that the multiplier is operating. The mm
operates for four cycles after the MA ends, regardless of slot. The ID of the instruction following
the DMULS.L instruction is stalled for 1 slot (see the description of the Multiply/Accumulate
instruction). The two MA stages of the DMULS.L instruction, when they contend with IF, split the
slot as described in section 7.2.1, Contention between Instruction Fetch (IF) and Memory Access
(MA).
When an instruction that does not use the multiplier comes after the DMULS.L instruction, the
DMULS.L instruction may be considered to be a five-stage pipeline instruction of IF, ID, EX,
MA, and MA. In such cases, it operates like a normal pipeline. When an instruction that uses the
multiplier come after the DMULS.L instruction, however, contention occurs with the multiplier,
so operation is different from normal.
This occurs in the following cases:
1. When a MAC.L instruction is located immediately after a DMULS.L instruction
2. When a MAC.W instruction is located immediately after a DMULS.L instruction
3. When a DMULS.L instruction is located immediately after another DMULS.L instruction
4. When a MULS.W instruction is located immediately after a DMULS.L instruction
5. When an STS (register) instruction is located immediately after a DMULS.L instruction
6. When an STS.L (memory) instruction is located immediately after a DMULS.L instruction
7. When an LDS (register) instruction is located immediately after a DMULS.L instruction
8. When an LDS.L (memory) instruction is located immediately after a DMULS.L instruction
DMULS.L
DMULU.L
MUL.L
Third instruction
Next instruction
Instruction A
Rm, Rn
Rm, Rn
Rm, Rn
......
Figure 7.72 Multiplication Instruction Pipeline
IF
ID
IF
EX
—
MA
ID
IF
MA
EX
ID
Rev. 5.00 Jun 30, 2004 page 481 of 512
mm
MA
EX
mm
WB
MA
Section 7 Pipeline Operation
mm
WB
REJ09B0171-0500O
mm
: Slot
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