HD6417041AVF16V Renesas Electronics America, HD6417041AVF16V Datasheet - Page 71

• Manufacturer Part Number: HD6417041AVF16V
• Description: IC SUPERH MCU ROMLESS 144QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7040r

Specifications of HD6417041AVF16V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 28.7MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

as the condition bit GT. The equation shown below defines the DC bit in this mode. However, VR
becomes a positive value when the result including the guard bit area exceeds the display range of
the destination operand.
When the PCMP instruction is executed in this mode, the DC bit becomes the same value as the T
bit that indicates the result of the SH core’s CMP/GT instruction. In this mode, the DC bit is
updated according to the above definition for instructions other than the PCMP instruction as well.
Signed Greater Than or Equal to Mode: CS2–CS0 = 101: The DC bit indicates whether or not
the source 1 data (signed) is greater than or equal to the source 2 data (signed) in the result of the
execution of a comparison instruction PCMP. For that reason, the PCMP instruction is executed
before checking the DC bit in this mode. This mode is similar to the Signed Greater Than mode
except for checking if the operands are the same. The equation shown below defines the DC bit in
this mode. However, VR becomes a positive value when the result, including the guard bit area,
exceeds the display range of the destination operand.
When the PCMP instruction is executed in this mode, the DC bit becomes the same value as the T
bit that indicates the result of the SuperH core’s CMP/GE instruction. In this mode, the DC bit is
updated according to the above definition for instructions other than the PCMP instruction as well.
4.7.4
The condition bits are set as follows:
The N (negative) bit has the same value as the DC bit when the CS bits specify negative mode.
When the operation result is negative, the N bit is 1. When the operation result is positive, the
N bit is 0.
The Z (zero) bit has the same value as the DC bit when the CS bits specify zero mode. When
the operation result is zero, the Z bit is 1. When the operation result is nonzero, the Z bit is 0.
The V (overflow) bit has the same value as the DC bit when the CS bits specify overflow
mode. When the operation result exceeds the bounds of the destination register without the
guard bits, the V bit is 1. Otherwise, the V bit is 0.
The GT (greater than) bit has the same value as the DC bit when the CS bits specify Signed
Greater Than mode. When the comparison result indicates the source 1 data is greater than the
source 2 data, the GT bit is 1. Otherwise, the GT bit is 0.
DC bit = ~ {(N bit ^ VR)|Z bit}
DC bit = ~ (N bit ^ VR)
Condition Bits
Rev. 5.00 Jun 30, 2004 page 55 of 512
Section 4 Instruction Features
REJ09B0171-0500O