HD6417041AVF16V Renesas Electronics America, HD6417041AVF16V Datasheet - Page 278
HD6417041AVF16V
Manufacturer Part Number
HD6417041AVF16V
Description
IC SUPERH MCU ROMLESS 144QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7040r
Specifications of HD6417041AVF16V
Core Processor
SH-2
Core Size
32-Bit
Speed
28.7MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417041AVF16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 6 Instruction Descriptions
6.1.69
Format
TRAPA
Description: Starts the trap exception processing. The PC and SR values are stored on the stack,
and the program branches to an address specified by the vector. The vector is a memory address
obtained by zero-extending the 8-bit immediate data and then quadrupling it. The PC is the start
address of the next instruction. TRAPA and RTE are both used together for system calls.
Operation:
Rev. 5.00 Jun 30, 2004 page 262 of 512
REJ09B0171-0500O
TRAPA(long i) /* TRAPA #imm */
{
}
long imm;
imm=(0x000000FF & i);
R[15]-=4;
Write_Long(R[15],SR);
R[15]-=4;
Write_Long(R[15],PC–2);
PC=Read_Long(VBR+(imm<<2))+4;
#imm
TRAPA (Trap Always): System Control Instruction
Abstract
PC/SR
(imm
4 + VBR)
Stack area,
PC
Code
11000011iiiiiiii
Cycle
8
T
Bit SH-1
—
Instructions
Applicable
SH-2
SH-
DSP
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