HD6417041AVF16V Renesas Electronics America, HD6417041AVF16V Datasheet - Page 441

• Manufacturer Part Number: HD6417041AVF16V
• Description: IC SUPERH MCU ROMLESS 144QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7040r

Specifications of HD6417041AVF16V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 28.7MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

4. Follow instructions that load an SH register (R0 to R15) from memory with instructions that
5. Do not place two instructions that use the multiplier consecutively (the PMULS instruction is
6. Avoid data transfers to memory or CPU core registers immediately after DSP unit data
7.3.3
Basic instructions are designed to execute in one cycle. One-cycle instructions include both
instructions that cause contention and instructions that do not. Operations and transfers that occur
between registers do not create contention.
There are instructions that require two or more cycles even when there is no contention.
Instructions that change the branch destination addresses, such as branch instructions or the like,
memory logic operation instructions, instructions that execute memory accesses twice or more,
such as some system control instructions, and instructions that have memory accesses and
multiplier accesses such as multiplication instructions and multiply and accumulate instructions,
(excluding PMULS) all take two or more cycles.
Instructions that require two or more cycles also include both instructions that cause contention
and instructions that do not.
To write efficient programs, it is essential to avoid contention, keep instruction execution speed
up, and use instructions with fewer stages.
do not use the same register as the load instruction’s destination register. This prevents
memory load contention caused by write backs (WB/DSP).
Note: The DSP registers (A0 to Y1) loaded in the previous cycle can be used in this cycle
excepted from this rule). Also try to keep accesses of MACH and MACL registers for getting
the results from the multiplier away from instructions that use the multiplier. This prevents
multiplier contention caused by multiplier accesses (mm).
operations from those registers storing the operation results. Avoid contention by placing
another instruction before the transfer.
Cycles
without causing any stalls.
Rev. 5.00 Jun 30, 2004 page 425 of 512
Section 7 Pipeline Operation
REJ09B0171-0500O