HD6417041AVF16V Renesas Electronics America, HD6417041AVF16V Datasheet - Page 87

IC SUPERH MCU ROMLESS 144QFP

HD6417041AVF16V

Manufacturer Part Number
HD6417041AVF16V
Description
IC SUPERH MCU ROMLESS 144QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7040r
Datasheets

Specifications of HD6417041AVF16V

Core Processor
SH-2
Core Size
32-Bit
Speed
28.7MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417041AVF16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
4.12.4
The condition bits are set as follows.
4.13
4.13.1
The DSP unit has a function for rounding 32-bit values to 16-bit values. When the value has guard
bits, 40 bits are rounded to 24 bits. When the rounding instruction is executed, H'0000 8000 is
added to the source operand and the bottom word is then cleared to zeros.
Rounding uses all bits of the source and destination operands. The action of the operation is the
same as for fixed decimal point operations and is executed in the DSP stage (the last stage) of the
pipeline.
The rounding instruction is unconditional. The DSR register’s DC, N, Z, V, and GT bits are thus
always updated according to the operation result.
Figure 4.17 shows the rounding flowchart. Figure 4.18 shows the rounding process definitions.
The N bit is the same as the result of the ALU integer operation. It is set to 1 for a negative
operation result and 0 for a positive operation result.
The Z bit is the same as the result of the ALU integer operation. It is set to 1 when the
operation result is zero; otherwise, the Z bit is 0.
The V bit is always 0.
The GT bit is the same as the result of the ALU integer operation. It is set 1 for a positive
operation result and otherwise to 0.
Operation Function
Condition Bits
Rounding
Rev. 5.00 Jun 30, 2004 page 71 of 512
Section 4 Instruction Features
REJ09B0171-0500O

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