HD6417041AVF16V Renesas Electronics America, HD6417041AVF16V Datasheet - Page 14

• Manufacturer Part Number: HD6417041AVF16V
• Description: IC SUPERH MCU ROMLESS 144QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7040r

Specifications of HD6417041AVF16V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 28.7MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 7 Pipeline Operation
7.1
7.2
7.3
7.4
Rev. 5.00 Jun 30, 2004 page xii of xiv
REJ09B0171-0500O
6.3.11 [if cc] PINC (Increment by 1 with Condition): DSP Arithmetic Operation
6.3.12 [if cc] PLDS (Load System Register): DSP System Control Instruction............. 347
6.3.13 PMULS (Multiply Signed by Signed): DSP Arithmetic Operation Instruction... 352
6.3.14 [if cc] PNEG (Negate): DSP Arithmetic Operation Instruction........................... 355
6.3.15 [if cc] POR (Logical OR): DSP Logical Operation Instruction ........................... 360
6.3.16 PRND (Rounding): DSP Arithmetic Operation Instruction................................. 365
6.3.17 [if cc] PSHA (Shift Arithmetically with Condition): DSP Arithmetic Shift
6.3.18 [if cc] PSHL (Shift Logically with Condition): DSP Logical Shift Instruction ... 377
6.3.19 [if cc] PSTS (Store System Register): DSP System Control Instruction ............. 385
6.3.20 [if cc]PSUB (Subtract with Condition): DSP Arithmetic Operation Instruction . 390
6.3.21 PSUB PMULS (Subtraction & Multiply Signed by Signed): DSP Arithmetic
6.3.22 PSUBC (Subtraction with Carry): DSP Arithmetic Operation Instruction .......... 400
6.3.23 [if cc] PXOR (Logical Exclusive OR): DSP Logical Operation Instruction........ 403
Basic Configuration of Pipelines ...................................................................................... 409
7.1.1
7.1.2
7.1.3
7.1.4
Contention......................................................................................................................... 413
7.2.1
7.2.2
7.2.3
7.2.4
Programming Guide.......................................................................................................... 422
7.3.1
7.3.2
7.3.3
Operation of Instruction Pipelines .................................................................................... 426
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
7.4.7
Instruction ............................................................................................................ 342
Instruction ............................................................................................................ 369
Operation Instruction ........................................................................................... 395
The Five-Stage Pipeline....................................................................................... 409
Slot and Pipeline Flow......................................................................................... 410
Slot Length........................................................................................................... 411
Number of Instruction Execution Cycles............................................................. 412
Contention between Instruction Fetch (IF) and Memory Access (MA)............... 413
Contention when the Previous Instruction’s Destination Register Is Used.......... 417
Multiplier Access Contention .............................................................................. 420
Contention between Memory Stores and DSP Operations .................................. 421
Types of Contention and Affected Instructions ................................................... 422
Increasing Instruction Execution Speed............................................................... 424
Cycles .................................................................................................................. 425
Data Transfer Instructions.................................................................................... 436
Arithmetic Instructions ........................................................................................ 439
Logic Operation Instructions ............................................................................... 483
Shift Instructions (Common) ............................................................................... 486
Branch Instructions .............................................................................................. 487
System Control Instructions................................................................................. 490
Exception Processing ........................................................................................... 498
............................................................................................ 409