HD6417041AVF16V Renesas Electronics America, HD6417041AVF16V Datasheet - Page 81
HD6417041AVF16V
Manufacturer Part Number
HD6417041AVF16V
Description
IC SUPERH MCU ROMLESS 144QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7040r
Specifications of HD6417041AVF16V
Core Processor
SH-2
Core Size
32-Bit
Speed
28.7MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
HD6417041AVF16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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operation is the same as for fixed decimal point operations and is executed in the DSP stage (the
last stage) of the pipeline.
Whenever a logical shift operation is executed, the DSR register’s DC, N, Z, V, and GT bits are
basically updated by the operation result. This is the same as for ALU logical operations. For
conditional instructions, condition bits are not updated even when the specified condition is
achieved and the instruction executed. For unconditional instructions, the bits are always updated
according to the operation result.
Figure 4.15 shows the logical shift operation flowchart.
DC Bit: The DC bit is set as follows depending on the mode specified by the CS bits.
Carry/borrow mode: CS2–CS0 = 000: The DC bit is the operation result, the value of the bit
pushed out by the last shift.
Negative Mode: CS2–CS0 = 001: In this mode, the DC bit is the same as the bit 31 of the
operation result. In this mode, the DC bit has the same value as bit N.
Zero Mode: CS2–CS0 = 010: The DC bit is 1 when the operation result is all zeros; otherwise,
the DC bit is 0. In this mode, the DC bit has the same value as bit Z.
Overflow Mode: CS2–CS0 = 011: The DC bit is always 0. In this mode, the DC bit has the
same value as bit V.
Shift amount data
(source 2)
Shift out
7g 0g 31
Left shift
Figure 4.15 Logical Shift Operation Flowchart
7g 0g 31 23 22 16 15
16 15
0
0
+16 to –16
5
imm2
Dz
0
0
< 0
7g 0g 31
0
Rev. 5.00 Jun 30, 2004 page 65 of 512
0
Update
Right shift
Section 4 Instruction Features
16 15
Shift out
GT
: Ignored
: Cleared to 0
REJ09B0171-0500O
Z
DSR
N V
0
DC
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