HD6417041AVF16V Renesas Electronics America, HD6417041AVF16V Datasheet - Page 80

• Manufacturer Part Number: HD6417041AVF16V
• Description: IC SUPERH MCU ROMLESS 144QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7040r

Specifications of HD6417041AVF16V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 28.7MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 4 Instruction Features
DC Bit: The DC bit is set as follows depending on the mode specified by the CS bits:
Condition Bits: The condition bits are set as follows:
Overflow Prevention Function (Saturation Operation): When the S bit of the SR register is set
to 1, the overflow prevention function is engaged for the ALU fixed decimal point arithmetic
operation executed by the DSP unit. When the operation result overflows, the maximum (positive)
or minimum (negative) value is stored.
4.11.2
Function: Logical shift operations use the top words of the source 1 operand and the destination
operand. As in ALU logical operations, the guard bits and bottom word of the operands are
ignored. The source 2 operand, which specifies the shift amount, is integer data. The source 2
operand is specified as a register or immediate operand. The valid amount of shift is –16 to +16.
Negative values are shifts to the right; positive values are shifts to the left. Between –32 and +31
can be specified for the source 2 operand, but only –16 to +16 is valid. When an invalid number is
specified, the results cannot be guaranteed. When an immediate value is specified for the shift
amount, the source 1 operand must be the same as the destination operand. The action of the
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Carry/Borrow Mode: CS2–CS0 = 000: The DC bit is the operation result, the value of the bit
pushed out by the last shift.
Negative Mode: CS2–CS0 = 001: Set to 1 for a negative operation result and 0 for a positive
operation result. In this mode, the DC bit has the same value as bit N.
Zero Mode: CS2–CS0 = 010: The DC bit is 1 when the operation result is zero; otherwise, the
DC bit is 0. In this mode, the DC bit has the same value as bit Z.
Overflow Mode: CS2–CS0 = 011: The DC bit is set to 1 by an overflow. In this mode, the DC
bit has the same value as bit V.
Signed Greater Than Mode: CS2–CS0 = 100: The DC bit is always 0. In this mode, the DC bit
has the same value as bit GT.
Signed Greater Than or Equal To Mode: CS2–CS0 = 101: The DC bit is always 0.
The N bit is the same as the result of the ALU fixed decimal point arithmetic operation. It is set
to 1 for a negative operation result and 0 for a positive operation result.
The Z bit is the same as the result of the ALU fixed decimal point arithmetic operation. It is set
to 1 when the operation result is zero; otherwise, the Z bit is 0.
The V bit is the same as the result of the ALU fixed decimal point arithmetic operation. It is set
to 1 for an overflow.
The GT bit is always 0.
Logical Shift Operations