IC MCU 128K 6MHZ A/D IT 64TQFP

ATMEGA103-6AI

Manufacturer Part NumberATMEGA103-6AI
DescriptionIC MCU 128K 6MHZ A/D IT 64TQFP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA103-6AI datasheets
 


Specifications of ATMEGA103-6AI

Core ProcessorAVRCore Size8-Bit
Speed6MHzConnectivitySPI, UART/USART
PeripheralsPOR, PWM, WDTNumber Of I /o32
Program Memory Size128KB (64K x 16)Program Memory TypeFLASH
Eeprom Size4K x 8Ram Size4K x 8
Voltage - Supply (vcc/vdd)4 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case64-TQFP, 64-VQFPFor Use WithATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS StatusContains lead / RoHS non-compliant  
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
Page 131
132
Page 132
133
Page 133
134
Page 134
135
Page 135
136
Page 136
137
Page 137
138
Page 138
139
Page 139
140
Page 140
141
Page 136/141

Download datasheet (3Mb)Embed
PrevNext
Instruction Set Summary (Continued)
Mnemonic
Operands
Description
LD
Rd, X
Load Indirect
LD
Rd, X+
Load Indirect and Post-increment
LD
Rd, -X
Load Indirect and Pre-decrement
LD
Rd, Y
Load Indirect
LD
Rd, Y+
Load Indirect and Post-increment
LD
Rd, -Y
Load Indirect and Pre-decrement
LDD
Rd, Y+q
Load Indirect with Displacement
LD
Rd, Z
Load Indirect
LD
Rd, Z+
Load Indirect and Post-increment
LD
Rd, -Z
Load Indirect and Pre-decrement
LDD
Rd, Z+q
Load Indirect with Displacement
LDS
Rd, k
Load Direct from SRAM
ST
X, Rr
Store Indirect
ST
X+, Rr
Store Indirect and Post-increment
ST
-X, Rr
Store Indirect and Pre-decrement
ST
Y, Rr
Store Indirect
ST
Y+, Rr
Store Indirect and Post-increment
ST
-Y, Rr
Store Indirect and Pre-decrement
STD
Y+q, Rr
Store Indirect with Displacement
ST
Z, Rr
Store Indirect
ST
Z+, Rr
Store Indirect and Post-increment
ST
-Z, Rr
Store Indirect and Pre-decrement
STD
Z+q, Rr
Store Indirect with Displacement
STS
k, Rr
Store Direct to SRAM
LPM
Load Program Memory
IN
Rd, P
In Port
OUT
P, Rr
Out Port
PUSH
Rr
Push Register on Stack
POP
Rd
Pop Register from Stack
BIT AND BIT-TEST INSTRUCTIONS
SBI
P, b
Set Bit in I/O Register
CBI
P, b
Clear Bit in I/O Register
LSL
Rd
Logical Shift Left
LSR
Rd
Logical Shift Right
ROL
Rd
Rotate Left through Carry
ROR
Rd
Rotate Right through Carry
ASR
Rd
Arithmetic Shift Right
SWAP
Rd
Swap Nibbles
BSET
s
Flag Set
BCLR
s
Flag Clear
BST
Rr, b
Bit Store from Register to T
BLD
Rd, b
Bit Load from T to Register
SEC
Set Carry
CLC
Clear Carry
SEN
Set Negative Flag
CLN
Clear Negative Flag
SEZ
Set Zero Flag
CLZ
Clear Zero Flag
SEI
Global Interrupt Enable
CLI
Global Interrupt Disable
SES
Set Signed Test Flag
CLS
Clear Signed Test Flag
SEV
Set Two’s Complement Overflow
CLV
Clear Two’s Complement Overflow
SET
Set T in SREG
CLT
Clear T in SREG
SEH
Set Half-carry Flag in SREG
CLH
Clear Half-carry Flag in SREG
NOP
No Operation
SLEEP
Sleep
WDR
Watchdog Reset
ATmega103(L)
136
Operation
Rd ← (X)
Rd ← (X), X ← X + 1
X ← X - 1, Rd ← (X)
Rd ← (Y)
Rd ← (Y), Y ← Y + 1
Y ← Y - 1, Rd ← (Y)
Rd ← (Y + q)
Rd ← (Z)
Rd ← (Z), Z ← Z + 1
Z ← Z - 1, Rd ← (Z)
Rd ← (Z + q)
Rd ← (k)
(X) ← Rr
(X) ← Rr, X ← X + 1
X ← X - 1, (X) ← Rr
(Y) ← Rr
(Y) ← Rr, Y ← Y + 1
Y ← Y - 1, (Y) ← Rr
(Y + q) ← Rr
(Z) ← Rr
(Z) ← Rr, Z ← Z + 1
Z ← Z - 1, (Z) ← Rr
(Z + q) ← Rr
(k) ← Rr
R0 ← (Z)
Rd ← P
P ← Rr
STACK ← Rr
Rd ← STACK
I/O(P,b) ← 1
I/O(P,b) ← 0
Rd(n+1) ← Rd(n), Rd(0) ← 0
Rd(n) ← Rd(n+1), Rd(7) ← 0
Rd(0) ← C, Rd(n+1) ← Rd(n), C ← Rd(7)
Rd(7) ← C, Rd(n) ← Rd(n+1), C ← Rd(0)
Rd(n) ← Rd(n+1), n = 0..6
Rd(3..0) ← Rd(7..4), Rd(7..4) ← Rd(3..0)
SREG(s) ← 1
SREG(s) ← 0
T ← Rr(b)
Rd(b) ← T
C ← 1
C ← 0
N ← 1
N ← 0
Z ← 1
Z ← 0
I ← 1
I ← 0
S ← 1
S ← 0
V ← 1
V ← 0
T ← 1
T ← 0
H ← 1
H ← 0
(see specific descr. for Sleep function)
(see specific descr. for WD Timer)
Flags
# Clocks
None
2
None
2
None
2
None
2
None
2
None
2
None
2
None
2
None
2
None
2
None
2
None
2
None
2
None
2
None
2
None
2
None
2
None
2
None
2
None
2
None
2
None
2
None
2
None
2
None
3
None
1
None
1
None
2
None
2
None
2
None
2
Z,C,N,V
1
Z,C,N,V
1
Z,C,N,V
1
Z,C,N,V
1
Z,C,N,V
1
None
1
SREG(s)
1
SREG(s)
1
T
1
None
1
C
1
C
1
N
1
N
1
Z
1
Z
1
I
1
I
1
S
1
S
1
V
1
V
1
T
1
T
1
H
1
H
1
None
1
None
1
None
1
0945I–AVR–02/07