IC MCU 128K 6MHZ A/D IT 64TQFP

ATMEGA103-6AI

Manufacturer Part NumberATMEGA103-6AI
DescriptionIC MCU 128K 6MHZ A/D IT 64TQFP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA103-6AI datasheets
 


Specifications of ATMEGA103-6AI

Core ProcessorAVRCore Size8-Bit
Speed6MHzConnectivitySPI, UART/USART
PeripheralsPOR, PWM, WDTNumber Of I /o32
Program Memory Size128KB (64K x 16)Program Memory TypeFLASH
Eeprom Size4K x 8Ram Size4K x 8
Voltage - Supply (vcc/vdd)4 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case64-TQFP, 64-VQFPFor Use WithATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS StatusContains lead / RoHS non-compliant  
ATMEGA103-6AC PDF datasheetATMEGA103-6AC PDF datasheet #2
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Page 41/141

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Timer/Counter0 Control
Register – TCCR0
Timer/Counter2 Control
Register – TCCR2
0945I–AVR–02/07
Bit
7
6
5
33 ($53)
–
PWM0
COM01
Read/Write
R
R/W
R/W
Initial Value
0
0
0
Bit
7
6
5
$25 ($45)
–
PWM2
COM21
Read/Write
R
R/W
R/W
Initial Value
0
0
0
• Bit 7 – Res: Reserved Bit
This bit is a reserved bit in the ATmega103(L) and always reads as zero.
• Bit 6 – PWM0/PWM2: Pulse Width Modulator Enable
When set (one), this bit enables PWM mode for Timer/Counter0 or Timer/Counter2.
This mode is described on page 43.
• Bits 5, 4 – COM01, COM00/COM21, COM20: Compare Output Mode, Bits 1 and 0
The COMn1 and COMn0 control bits determine any output pin action following a com-
pare match in Timer/Counter2. Any output pin actions affect pins PB4 (OC0/PWM0) or
PB7 (OC2/PWM2). Since this is an alternative function to an I/O port, the corresponding
direction control bit must be set (one) to control an output pin. The control configuration
is shown in Table 10.
Table 10. Compare Mode Select
COMn1
COMn0
Description
0
0
Timer/Counter disconnected from output pin OCn/PWMn
0
1
Toggle the OCn/PWMn output line.
1
0
Clear the OCn/PWMn output line (to zero).
1
1
Set the OCn/PWMn output line (to one).
Note:
n = 0 or 2
In PWM mode, these bits have a different function. Refer to Table 13 for a detailed
description.
• Bit 3 – CTC0/CTC2: Clear Timer/Counter on Compare Match
When the CTC0 or CTC2 control bit is set (one), the Timer/Counter is reset to $00 in the
CPU clock cycle after a compare match. If the control bit is cleared, the Timer continues
counting and is unaffected by a compare match. Since the compare match is detected in
the CPU clock cycle following the match, this function will behave differently when a
prescaling higher than 1 is used for the Timer. When a prescaling of 1 is used and the
Compare Register is set to C, the Timer will count as follows if CTC0/2 is set:
... | C-2 | C-1 | C | 0 | 1 | ...
When the prescaler is set to divide by 8, the Timer will count like this:
... | C-2, C-2, C-2, C-2, C-2, C-2, C-2, C-2 | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, 0,
0, 0, 0, 0, 0, 0 | 1, 1, 1, ...
ATmega103(L)
4
3
2
1
COM00
CTC0
CS02
CS01
R/W
R/W
R/W
R/W
0
0
0
0
4
3
2
1
COM20
CTC2
CS22
CS21
R/W
R/W
R/W
R/W
0
0
0
0
0
CS00
TCCR0
R/W
0
0
CS20
TCCR2
R/W
0
41

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