IC MCU 128K 6MHZ A/D IT 64TQFP

ATMEGA103-6AI

Manufacturer Part NumberATMEGA103-6AI
DescriptionIC MCU 128K 6MHZ A/D IT 64TQFP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA103-6AI datasheets
 

Specifications of ATMEGA103-6AI

Core ProcessorAVRCore Size8-Bit
Speed6MHzConnectivitySPI, UART/USART
PeripheralsPOR, PWM, WDTNumber Of I /o32
Program Memory Size128KB (64K x 16)Program Memory TypeFLASH
Eeprom Size4K x 8Ram Size4K x 8
Voltage - Supply (vcc/vdd)4 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case64-TQFP, 64-VQFPFor Use WithATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS StatusContains lead / RoHS non-compliant  
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Page 31
32
Page 32
33
Page 33
34
Page 34
35
Page 35
36
Page 36
37
Page 37
38
Page 38
39
Page 39
40
Page 40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
Page 35/141

Download datasheet (3Mb)Embed
PrevNext
Timer/Counter Interrupt Flag
Register – TIFR
0945I–AVR–02/07
Bit
7
6
$36 ($56)
OCF2
TOV2
ICF1
Read/Write
R/W
R/W
R/W
Initial Value
0
0
• Bit 7 – OCF2: Output Compare Flag 2:
The OCF2 bit is set (one) when compare match occurs between Timer/Counter2 and
the data in OCR2 – Output Compare Register 2. OCF2 is cleared by hardware when
executing the corresponding interrupt handling vector. Alternatively, OCF2 is cleared by
writing a logical “1” to the flag. When the I-bit in SREG, and OCIE2 (Timer/Counter2
Compare Interrupt Enable) and the OCF2 are set (one), the Timer/Counter2 Output
Compare interrupt is executed.
• Bit 6 – TOV2: Timer/Counter2 Overflow Flag
The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared
by hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV2 is cleared by writing a logical “1” to the flag. When the I-bit in SREG, and TOIE2
(Tim er/Co un ter1 Ove rflow Inte rrup t En able) an d TO V2 a re set (o ne) , th e
Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when
Timer/Counter2 advances from $00.
• Bit 5 – ICF1: Input Capture Flag 1
The ICF1 bit is set (one) to flag an Input Capture event, indicating that the
Timer/Counter1 value has been transferred to the Input Capture Register (ICR1). ICF1
is cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, ICF1 is cleared by writing a logical “1” to the flag. When the SREG I-bit,
TICIE1 (Timer/Counter1 Input Capture Interrupt Enable) and ICF1 are set (one), the
Timer/Counter1 Capture interrupt is executed.
• Bit 4 – OCF1A: Output Compare Flag 1A
The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1
and the data in OCR1A – Output Compare Register 1A. OCF1A is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, OCF1A is
cleared by writing a logical “1” to the flag. When the I-bit in SREG and OCIE1A
(Timer/Counter1 Compare Interrupt Enable) and the OCF1A are set (one), the
Timer/Counter1 Compare A Match interrupt is executed.
• Bit 3 – OCF1B: Output Compare Flag 1B
The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1
and the data in OCR1B – Output Compare Register 1B. OCF1B is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, OCF1B is
cleared by writing a logical “1” to the flag. When the I-bit in SREG and OCIE1B
(Timer/Counter1 Compare Match Interrupt Enable) and the OCF1B are set (one), the
Timer/Counter1 Compare B Match interrupt is executed.
• Bit 2 – TOV1: Timer/Counter1 Overflow Flag
The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by
hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV1 is cleared by writing a logical “1” to the flag. When the I-bit in SREG and TOIE1
ATmega103(L)
5
4
3
2
OCF1A
OCF1B
TOV1
OCF0
R/W
R/W
R/W
R/W
0
0
0
0
1
0
TOV0
TIFR
R/W
0
0
35