ATMEGA103-6AI Atmel, ATMEGA103-6AI Datasheet - Page 17

IC MCU 128K 6MHZ A/D IT 64TQFP

ATMEGA103-6AI

Manufacturer Part Number
ATMEGA103-6AI
Description
IC MCU 128K 6MHZ A/D IT 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA103-6AI

Core Processor
AVR
Core Size
8-Bit
Speed
6MHz
Connectivity
SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
32
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
EEPROM Data Memory
Memory Access Times
and Instruction
Execution Timing
0945I–AVR–02/07
Program execution continues at address PC + k + 1. The relative address k is -2048 to
2047.
The EEPROM memory is organized as a separate Data space in which single bytes can
be read and written. The EEPROM has an endurance of at least 100,000 write/erase
cycles. The access between the EEPROM and the CPU is described on page 57 speci-
fying the EEPROM Address Register, the EEPROM Data Register and the EEPROM
Control Register.
This section describes the general access timing concepts for instruction execution and
internal memory access.
The AVR CPU is driven by the System Clock Ø, directly generated from the external
clock crystal for the chip. No internal clock division is used.
Figure 20 shows the parallel instruction fetches and instruction executions enabled by
the Harvard architecture and the fast-access Register File concept. This is the basic
pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results
for functions per cost, functions per clocks and functions per power unit.
Figure 20. The Parallel Instruction Fetches and Instruction Executions
System Clock Ø
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 21 shows the internal timing concept for the Register File. In a single clock cycle,
an ALU operation using two register operands is executed and the result is stored back
to the destination register.
Figure 21. Single Cycle ALU Operation
System Clock Ø
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
ATmega103(L)
T1
T2
T3
T1
T2
T3
T4
T4
17

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