IC MCU 128K 6MHZ A/D IT 64TQFP

ATMEGA103-6AI

Manufacturer Part NumberATMEGA103-6AI
DescriptionIC MCU 128K 6MHZ A/D IT 64TQFP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA103-6AI datasheets
 


Specifications of ATMEGA103-6AI

Core ProcessorAVRCore Size8-Bit
Speed6MHzConnectivitySPI, UART/USART
PeripheralsPOR, PWM, WDTNumber Of I /o32
Program Memory Size128KB (64K x 16)Program Memory TypeFLASH
Eeprom Size4K x 8Ram Size4K x 8
Voltage - Supply (vcc/vdd)4 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case64-TQFP, 64-VQFPFor Use WithATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS StatusContains lead / RoHS non-compliant  
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Page 22/141

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RAM Page Z Select Register –
RAMPZ
MCU Control Register –
MCUCR
ATmega103(L)
22
instruction and it is incremented by 2 when an address is popped from the Stack with
return from subroutine RET or return from interrupt RETI.
Bit
7
6
5
$3B ($5B)
Read/Write
R
R
R
Initial Value
0
0
0
The RAMPZ Register is normally used to select which 64K RAM page is accessed by
the Z pointer. As the ATmega103(L) does not support more than 64K of SRAM memory,
this register is used only to select which page in the Program memory is accessed when
the ELPM instruction is used. The different settings of the RAMPZ0 bit have the follow-
ing effects:
RAMPZ0 = 0:
Program memory address $0000 - $7FFF (lower 64K bytes) is
accessed by ELPM
RAMPZ0 = 1:
Program memory address $8000 - $FFFF (higher 64K bytes) is
accessed by ELPM
Note that LPM is not affected by the RAMPZ setting.
The MCU Control Register contains control bits for general MCU functions.
Bit
7
6
5
$35 ($55)
SRE
SRW
SE
Read/Write
R/W
R/W
R/W
Initial Value
0
0
0
• Bit 7 – SRE: External SRAM Enable
When the SRE bit is set (one), the external Data SRAM is enabled, and the pin functions
AD0 - 7 (Port A), and A8 - 15 (Port C) are activated as the alternate pin functions. Then
the SRE bit overrides any pin direction settings in the respective Data Direction Regis-
ters. When the SRE bit is cleared (zero), the external Data SRAM is disabled and the
normal pin and data direction settings are used.
• Bit 6 – SRW: External SRAM Wait State
When the SRW bit is set (one), a one-cycle wait state is inserted in the external Data
SRAM access cycle. When the SRW bit is cleared (zero), the external Data SRAM
access is executed with a three-cycle scheme. See Figure 51 on page 85 and Figure 52
on page 85.
• Bit 5 – SE: Sleep Enable
The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the sleep mode unless it is the pro-
grammer’s purpose, it is recommended to set the Sleep Enable (SE) bit just before the
execution of the SLEEP instruction.
4
3
2
1
0
RAMPZ0
R
R
R
R
R/W
0
0
0
0
0
4
3
2
1
0
SM1
SM0
R/W
R/W
R
R
R
0
0
0
0
0
RAMPZ
MCUCR
0945I–AVR–02/07