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ATMEGA103-6AI
ATMEGA103-6AI | |
|---|---|
| Manufacturer Part Number | ATMEGA103-6AI |
| Description | IC MCU 128K 6MHZ A/D IT 64TQFP |
| Manufacturer | Atmel |
| Series | AVR® ATmega |
| ATMEGA103-6AI datasheets |
|
Specifications of ATMEGA103-6AI | |||
|---|---|---|---|
| Core Processor | AVR | Core Size | 8-Bit |
| Speed | 6MHz | Connectivity | SPI, UART/USART |
| Peripherals | POR, PWM, WDT | Number Of I /o | 32 |
| Program Memory Size | 128KB (64K x 16) | Program Memory Type | FLASH |
| Eeprom Size | 4K x 8 | Ram Size | 4K x 8 |
| Voltage - Supply (vcc/vdd) | 4 V ~ 5.5 V | Data Converters | A/D 8x10b |
| Oscillator Type | Internal | Operating Temperature | -40°C ~ 85°C |
| Package / Case | 64-TQFP, 64-VQFP | For Use With | ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU |
| Lead Free Status / RoHS Status | Contains lead / RoHS non-compliant | ||
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PrevNext
EEPROM Read/Write
Access
EEPROM Address Register –
EEARH, EEARL
EEPROM Data Register –
EEDR
EEPROM Control Register –
EECR
0945I–AVR–02/07
The EEPROM Access Registers are accessible in the I/O space.
The write access time is in the range of 2.5 - 4 ms, depending on the V
self-timing function lets the user software detect when the next byte can be written. A
special EEPROM Ready interrupt can be set to trigger when the EEPROM is ready to
accept new data.
In order to prevent unintentional EEPROM writes, a specific write procedure must be fol-
lowed. Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed. When it is read, the CPU is halted for four clock cycles.
Bit
15
14
13
$1F ($3F)
–
–
–
$1E ($3E)
EEAR7
EEAR6
EEAR5
7
6
5
Read/Write
R
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
The EEPROM Address Registers (EEARH and EEARL) specify the EEPROM address
in the 4 KB EEPROM space. The EEPROM Data bytes are addressed linearly between
0 and 4095.
Bit
7
6
5
$1D ($3D)
MSB
Read/Write
R/W
R/W
R/W
Initial Value
0
0
0
• Bits 7..0 – EEDR7..0: EEPROM Data:
For the EEPROM write operation, the EEDR Register contains the data to be written to
the EEPROM in the address given by the EEAR Register. For the EEPROM read oper-
ation, the EEDR contains the data read out from the EEPROM at the address given by
EEAR.
Bit
7
6
5
$1C ($3C)
–
–
–
Read/Write
R
R
R
Initial Value
0
0
0
• Bits 7..4 – Res: Reserved Bits
These bits are reserved bits in the ATmega103(L) and will always be read as zero.
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
When the I-bit in SREG and EERIE are set (one), the EEPROM Ready interrupt is
enabled. When cleared (zero), the interrupt is disabled. The EEPROM Ready interrupt
constantly generates an interrupt request when EEWE is cleared (zero).
ATmega103(L)
12
11
10
9
–
EEAR11
EEAR10
EEAR9
EEAR4
EEAR3
EEAR2
EEAR1
4
3
2
1
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
4
3
2
1
R/W
R/W
R/W
R/W
0
0
0
0
4
3
2
1
–
EERIE
EEMWE
EEWE
R
R/W
R/W
R/W
0
0
0
0
voltages. A
CC
8
EEAR8
EEARH
EEAR0
EEARL
0
R/W
R/W
0
0
0
LSB
EEDR
R/W
0
0
EERE
EECR
R/W
0
57
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