IC MCU 128K 6MHZ A/D IT 64TQFP

ATMEGA103-6AI

Manufacturer Part NumberATMEGA103-6AI
DescriptionIC MCU 128K 6MHZ A/D IT 64TQFP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA103-6AI datasheets
 

Specifications of ATMEGA103-6AI

Core ProcessorAVRCore Size8-Bit
Speed6MHzConnectivitySPI, UART/USART
PeripheralsPOR, PWM, WDTNumber Of I /o32
Program Memory Size128KB (64K x 16)Program Memory TypeFLASH
Eeprom Size4K x 8Ram Size4K x 8
Voltage - Supply (vcc/vdd)4 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case64-TQFP, 64-VQFPFor Use WithATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS StatusContains lead / RoHS non-compliant  
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Page 20/141

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Status Register – SREG
ATmega103(L)
20
Table 2. ATmega103(L) I/O Space (Continued)
I/O Address (SRAM
Address)
Name
$06 ($26)
ADCSR
$05 ($25)
ADCH
$04 ($24)
ADCL
$03 ($23)
PORTE
$02 ($22)
DDRE
$01 ($21)
PINE
$00 ($20)
PINF
Note:
Reserved and unused locations are not shown in the table.
All the different ATmega103(L) I/Os and peripherals are placed in the I/O space. The dif-
ferent I/O locations are directly accessed by the IN and OUT instructions transferring
data between the 32 general purpose working registers and the I/O space. I/O Registers
within the address range $00 - $1F are directly bit-accessible using the SBI and CBI
instructions. In these registers, the value of single bits can be checked by using the
SBIS and SBIC instructions. Refer to the “Instruction Set Summary” on page 135 for
more details. When using the I/O specific instructions IN and OUT, the I/O Register
address $00 - $3F are used. When addressing I/O Registers as SRAM, $20 must be
added to this address. All I/O Register addresses throughout this document are shown
with the SRAM address in parentheses.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the Status Flags are cleared by writing a logical “1” to them. Note that the CBI
and SBI instructions will operate on all bits in the I/O Register, writing a one back into
any flag read as set, thus clearing the flag. The CBI and SBI instructions work with reg-
isters $00 to $1F only.
The different I/O and peripherals control registers are explained in the following
sections.
The AVR Status Register (SREG) at I/O space location $3F ($5F) is defined as:
Bit
7
6
5
$3F ($5F)
I
T
H
Read/Write
R/W
R/W
R/W
Initial Value
0
0
0
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set (one) for the interrupts to be enabled. The
individual interrupt enable control is then performed in separate control registers. If the
Global Interrupt Enable Register is cleared (zero), none of the interrupts are enabled
independent of the individual interrupt enable settings. The I-bit is cleared by hardware
after an interrupt has occurred and is set by the RETI instruction to enable subsequent
interrupts.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source
and destination for the operated bit. A bit from a register in the Register File can be cop-
Function
ADC Control and Status Register
ADC Data Register High
ADC Data Register Low
Data Register, Port E
Data Direction Register, Port E
Input Pins, Port E
Input Pins, Port F
4
3
2
1
S
V
N
Z
R/W
R/W
R/W
R/W
0
0
0
0
0
C
SREG
R/W
0
0945I–AVR–02/07