IC MCU 128K 6MHZ A/D IT 64TQFP

ATMEGA103-6AI

Manufacturer Part NumberATMEGA103-6AI
DescriptionIC MCU 128K 6MHZ A/D IT 64TQFP
ManufacturerAtmel
SeriesAVR® ATmega
ATMEGA103-6AI datasheets
 


Specifications of ATMEGA103-6AI

Core ProcessorAVRCore Size8-Bit
Speed6MHzConnectivitySPI, UART/USART
PeripheralsPOR, PWM, WDTNumber Of I /o32
Program Memory Size128KB (64K x 16)Program Memory TypeFLASH
Eeprom Size4K x 8Ram Size4K x 8
Voltage - Supply (vcc/vdd)4 V ~ 5.5 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case64-TQFP, 64-VQFPFor Use WithATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS StatusContains lead / RoHS non-compliant  
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Page 66/141

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UART
Data Transmission
ATmega103(L)
66
The ATmega103(L) features a full duplex (separate Receive and Transmit Registers)
Universal Asynchronous Receiver and Transmitter (UART). The main features are:
Baud Rate Generator that can Generate a large Number of Baud Rates (bps)
High Baud Rates at Low XTAL Frequencies
8 or 9 Bits Data
Noise Filtering
OverRun Detection
Framing Error Detection
False Start Bit Detection
Three separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
A block schematic of the UART Transmitter is shown in Figure 41.
Data transmission is initiated by writing the data to be transmitted to the UART I/O Data
Register, UDR. Data is transferred from UDR to the Transmit Shift Register when:
A new character has been written to UDR after the stop bit from the previous
character has been shifted out. The Shift Register is loaded immediately.
A new character has been written to UDR before the stop bit from the previous
character has been shifted out. The Shift Register is loaded when the stop bit of the
character currently being transmitted has been shifted out.
If the 10(11)-bit Transmit Shift Register is empty, data is transferred from UDR to the
Shift Register. At this time the UDRE (UART Data Register Empty) bit in the UART Sta-
tus Register, USR, is set. When this bit is set (one), the UART is ready to receive the
next character. Writing to UDR clears UDRE. At the same time as the data is transferred
from UDR to the 10(11)-bit Shift Register, bit 0 of the Shift Register is cleared (start bit)
and bit 9 or 10 is set (stop bit). If 9-bit data word is selected (the CHR9 bit in the UART
Control Register, UCR is set), the TXB8 bit in UCR is transferred to bit 9 in the Transmit
Shift Register.
0945I–AVR–02/07