ATMEGA103-6AI Atmel, ATMEGA103-6AI Datasheet - Page 71

IC MCU 128K 6MHZ A/D IT 64TQFP

ATMEGA103-6AI

Manufacturer Part Number
ATMEGA103-6AI
Description
IC MCU 128K 6MHZ A/D IT 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA103-6AI

Core Processor
AVR
Core Size
8-Bit
Speed
6MHz
Connectivity
SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
32
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
string(70) "Class: /home/ecomp/master.elcodis.git/htdocs/inc/../Doc.php not found!" string(70) "Class: /home/ecomp/master.elcodis.git/htdocs/inc/../Doc.php not found!" string(70) "Class: /home/ecomp/master.elcodis.git/htdocs/inc/../Doc.php not found!" string(70) "Class: /home/ecomp/master.elcodis.git/htdocs/inc/../Doc.php not found!"
UART Control Register – UCR
0945I–AVR–02/07
• Bit 4 – FE: Framing Error
This bit is set if a Framing Error condition is detected, i.e., when the stop bit of an incom-
ing character is zero.
The FE bit is cleared when the stop bit of received data is one.
• Bit 3 – OR: OverRun
This bit is set if an OverRun condition is detected, i.e., when a character already present
in the UDR Register is not read before the next character is transferred from the
Receiver Shift Register. The OR bit is buffered, which means that it will be set once the
valid data still in UDRE is read.
The OR bit is cleared (zero) when data is received and transferred to UDR.
• Bits 2..0 – Res: Reserved Bits
These bits are reserved bits in the ATmega103(L) and will always read as zero.
• Bit 7 – RXCIE: RX Complete Interrupt Enable
When this bit is set (one), a setting of the RXC bit in USR will cause the Receive Com-
plete Interrupt routine to be executed, provided that global interrupts are enabled.
• Bit 6 – TXCIE: TX Complete Interrupt Enable
When this bit is set (one), a setting of the TXC bit in USR will cause the Transmit Com-
plete Interrupt routine to be executed, provided that global interrupts are enabled.
• Bit 5 – UDRIE: UART Data Register Empty Interrupt Enable
When this bit is set (one), a setting of the UDRE bit in USR will cause the UART Data
Register Empty Interrupt routine to be executed, provided that global interrupts are
enabled.
• Bit 4 – RXEN: Receiver Enable
This bit enables the UART Receiver when set (one). When the Receiver is disabled, the
RXC, OR and FE Status Flags cannot become set. If these flags are set, turning off
RXEN does not cause them to be cleared.
• Bit 3 – TXEN: Transmitter Enable
This bit enables the UART Transmitter when set (one). When disabling the Transmitter
while transmitting a character, the Transmitter is not disabled before the character in the
Shift Register plus any following character in UDR has been completely transmitted.
• Bit 2 – CHR9: 9-bit Characters
When this bit is set (one), transmitted and received characters are nine bits long, plus
start and stop bits. The ninth bit is read and written by using the RXB8 and TXB8 bits in
UCR, respectively. The ninth data bit can be used as an extra stop bit or a parity bit.
Bit
$0A ($2A)
Read/Write
Initial Value
RXCIE
R/W
7
0
TXCIE
R/W
6
0
UDRIE
R/W
5
0
RXEN
R/W
4
0
TXEN
R/W
3
0
CHR9
R/W
2
0
ATmega103(L)
RXB8
R
1
1
TXB8
W
0
0
UCR
71

Related parts for ATMEGA103-6AI