IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 10

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

1–4
Figure 1–1. POS-PHY Level 4 MegaCore Function as Link Layer Configuration
Figure 1–2. POS-PHY Level 4 MegaCore Function as PHY Layer Configuration
POS-PHY Level 4 MegaCore Function User Guide
Interfaces & Protocols
10 GbitE MAC
POS Framer
OC-192
or
OC-192 or
10 GbitE
SPI-4.2 Interface
Figure 1–1
the link layer in an Altera FPGA device.
Figure 1–2
the PHY layer in an Altera FPGA device.
The following three interfaces support the POS-PHY Level 4 MegaCore function:
■
■
■
You can use multiple Atlantic interfaces, but the SPI-4.2 interface only supports a
single transmitter and a single receiver.
SPI-4.2 Interface
The SPI-4.2 interface is an external interface protocol developed by the Optical
Internetworking Forum (OIF). The SPI-4.2 interface features a high-speed data
portion and a FIFO buffer status portion. The high-speed portion comprises a 16-bit
data bus, a 1-bit control line, and a double data rate (DDR) clock. The FIFO buffer
status portion comprises a 2-bit status channel and a clock.
Figure 1–3
Figure 1–3. SPI-4.2 Top-Level View
SPI-4.2 interface
Atlantic
Avalon
POS-PHY Level 4
POS-PHY Level 4
®
shows a full-duplex POS-PHY Level 4 MegaCore function configured for
shows a full-duplex POS-PHY Level 4 MegaCore function configured for
shows a full-duplex SPI-4.2 configuration.
™
Transmitter
Memory-Mapped (Avalon-MM) interface.
Receiver
interface
Framer or MAC
Logic
Atlantic Interface
Atlantic Interface
Transmitter
Source
FPGA
tdat[15:0]
tstat[1:0]
User Packet
Processing
tdclk
tsclk
POS-PHY Level 4
POS-PHY Level 4
tctl
FPGA
Transmitter
Receiver
SPI-4.2 Interface
rdclk
rctl
rdat[15:0]
rsclk
rstat[1:0]
Interface
Switch
Receiver
Chapter 1: About This MegaCore Function
Sink
December 2010 Altera Corporation
Packet
Classifier
Switch
Fabric
General Description