IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 48

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

4–8
POS-PHY Level 4 MegaCore Function User Guide
1
The status PHY block aligns rstat to either the positive or negative edge of rsclk
depending on the input value of the ctl_rs_statedge signal. This block also
implements a clock-crossing FIFO buffer between the rsclk and rxsys_clk domains.
The status FSM block (rx_stat_proc_fsm) is enabled when the clock-crossing FIFO
buffer of the status PHY block has available space. When enabled, this block generates
the next words in the status frame.
If the clock-crossing FIFO buffer underflows or overflows because of an incorrect
configuration, if the ctl_ry_rsfrm signal is set, or if the rsfrm bit in the Avalon
Memory-Mapped (Avalon-MM) interface is set, the finite state machine outputs ‘11’
continuously and the stat_ry_disabled signal is asserted.
Framing, calendar select word, and DIP are generated locally, but the actual status for
each calendar slot is provided on request by the status register (rx_stat_proc_reg)
block, and either the status calculator (rx_stat_calc) or status hold (rx_stat_hold)
blocks.
Given a calendar slot number, the status register block determines which port's status
belongs in the slot according to the calendar that it stores. When the asymmetric port
support parameter is turned off, the port number corresponds with the slot number,
(that is, slot one is port one, and so on). When the asymmetric port support parameter
is turned on, a programmable calendar is stored in memory, and the port
corresponding to the slot is looked up.
If the asymmetric port support parameter is turned on, the Avalon-MM registers must
be programmed prior to releasing the rsfrm bit (refer to
MM Interface Register Map” on page
The port number is provided with a request signal to both the status calculator and
status hold blocks, but only the output of one block, according to the value of the
ctl_ry_fifostatoverride input, is sent to the status FSM block to be inserted into the
outgoing status frame. In the individual buffers mode, the ctl_ry_fifostatoverride
input is forced low to always select the calculated value. In the shared buffer with
embedded addressing mode, the ctl_ry_fifostatoverride input is set according to
the option selected in IP Toolbench for the status source parameter. If the user-
controlled option is selected, you must write buffer status per-port into the status hold
block via the external status interface. Otherwise, the interface is ignored and the
calculated value is used. This external control interface features an 8-bit address bus, a
2-bit status port value, and a valid signal (refer to
4–29).
Figure
Chapter 4: Functional Description—Receiver
Appendix E
4–3).
December 2010 Altera Corporation
and the
Block Description
“Avalon-
®