IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 96

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

5–24
Table 5–9. Scheduler Control and Status
Avalon-MM Interface Register Map
POS-PHY Level 4 MegaCore Function User Guide
ctl_td_mb1[10:0]
ctl_td_mb2[10:0]
ctl_td_
switchmode[1:0]
Signal
Table 5–10
Input
Input
Input -
Static reset
Direction
lists the Avalon-MM interface registers.
tdint_clk
Clock Domain
Maximum number of bytes that can be transmitted when the
downstream FIFO buffer is starving. This number does not
imply that a control word is inserted. Units are in bytes.
Supports 0 to 2,032 bytes in 16-byte increments. This port is
absent if you turn on Shared Buffer with Embedded
Addressing.
Maximum number of bytes that can be transmitted when the
downstream FIFO buffer is hungry. This number does not
imply that a control word is inserted. Units are in bytes.
Supports 0 to 2,032 bytes in 16-byte increments. This port is
absent if you turn on Shared Buffer with Embedded
Addressing.
This input determines the port switching behavior of the
scheduler.
■
■
■
■
■
■
■
■
The scheduler always makes a port switch decision when
ctl_td_burstlen data is sent, or when an EOP is sent.
Next credits are held in a table for all ports, and are
incremented by status updates.
Current credits are stored in a separate register for a single
port while it is serviced, and become stale because status
updates do not increment the value.
A port is only eligible for scheduling if there are greater
than or equal to ctl_td_burstlen next credits available,
and greater than or equal to ctl_td_burstlen data
available in the corresponding Atlantic FIFO buffer.
When ‘00’ (switch on EOP is turned off) the scheduler
switches when less than ctl_td_burstlen current
credits are available, or less than ctl_td_burstlen data
is available in the Atlantic buffer.
When ‘01’ (switch on EOP is turned on), the scheduler
switches when less than ctl_td_burstlen current
credits are available, or less than ctl_td_burstlen data
is available in the Atlantic buffer, or an EOP is sent.
When ‘10’ or ‘11’, the scheduler switches when
ctl_td_burstlen data is sent, or an EOP is sent.
In the IP Toolbench top-level file, the upper bit is always
tied to zero, and the lower bit is tied depending on the value
of the switch on end of packet feature. This port is absent if
you turn on Shared Buffer with Embedded Addressing.
Only change at reset.
Chapter 5: Functional Description—Transmitter
Description
December 2010 Altera Corporation
Avalon-MM Interface Register Map