IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 136

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

G–2
Table G–1. Receiver Signal Changes (Part 1 of 3)
POS-PHY Level 4 MegaCore Function User Guide
rdclk
rctl
rdat[15:0]
rsclk
rstat[1:0]
rdint_clk
rdint_reset_n
rxsys_clk
rxsys_reset_n
rxreset_n
rxinfo_aot[12:0]
aN_arxclk
aN_arxreset_n
aN_arxdav
aN_arxena
aN_arxdat
aN_arxval
aN_arxsop
aN_arxeop
aN_arxmty
aN_arxerr
aN_arxadr
ctl_ax_ftl
ctl_ax_fifo_eopdav
err_aN_fifo_parityN
stat_aN_fifo_emptyN
err_ry_fifo_oflwN
ctl_ry_errchk_chkpkt
Version 2.4.x and 2.3.x Signal
Name
Table G–1
MegaWizard
applicable), and notes explaining the changes.
shows the new v2.4.x and 2.3.x receiver signal names as they exist in the
rdclk
rctl
rdat[15:0]
rsclk
rstat[1:0]
rrefclk
–
a0_arxclk
–
rxreset_n
rxinfo_aot[15:0]
aN_arxclk
aN_arxreset_n
aN_arxdav
aN_arxena
aN_arxdat
aN_arxval
aN_arxsop
aN_arxeop
aN_arxmty
aN_arxerr
aN_arxadr
ctl_a0_rxftl
ctl_xx_fifo_eopdav
–
stat_a0_rxfifo_empty
err_xx_rxfifo_oflw
ctl_xx_errchk_chpkt
®
Plug-In top-level file, their equivalent v2.2.x signal names (if
Version 2.2.x Signal Name
No change.
Clock derived from rdclk. Signals infixed by
_rd_ are synchronous to this domain.
New. Tied high in the IP Toolbench top-level file.
Refer to
usage.
System clock. Signals infixed by _ry_ are
synchronous to this clock. Refer to
Structure” on page 4–10
New. Tied high in the IP Toolbench top-level file.
Refer to
usage.
No change. Resets all domains.
Change in port width.
No change.
Tied high in the IP Toolbench top-level file.
No change.
New.
No change.
In version 2.2.x, this signal is in the rrefclk
domain; in version 2.3.0, this signal is in the
rxsys_clk domain.
No change.
“Clock Structure” on page 4–10
“Clock Structure” on page 4–10
Appendix G: Conversion from v2.2.x
December 2010 Altera Corporation
Notes
for usage.
Receiver Signals
“Clock
for
for