IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 47

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description—Receiver
Block Description
December 2010 Altera Corporation
Status Processor
The shared buffer and the logic support up to 256 ports. If Atlantic error checking is
enabled, 256 ports are still supported by the MegaCore function, but the logic for error
checking uses only the minimum amount of logic required to support the number of
ports chosen as a parameter. The port width field remains fixed for 256 ports and
unused address bits are passed through unaffected. For example, if a variation has 4
ports, only the lower 2 address bits are used for error checking—data received for port
6 is checked as though it is for port 2. This allows unused upper address bits to be
used for packet classification.
The single FIFO buffer with embedded addressing supports interleaved packets. An
interleaved packet occurs when, for example, a packet from port 2 is sent, and then a
packet from port 3 is sent before port 2 has received the EOP indication. This
interleaving is achieved by changing the aN_arxadr in the middle of the packet.
The shared buffer with embedded addressing mode is useful if you intend to handle
buffering outside of the MegaCore function. To support user-defined external
buffering, a fully exposed status interface is provided, but requires that the status
channel override (status source parameter) be enabled. Normally, the shared buffer
with embedded addressing fill level is compared against the global almost empty
(AE) and almost full (AF) values to produce the status information for all ports on the
status channel. With the override feature, you can set the FIFO buffer status
information values on a per-port basis.
Individual Buffers
When the individual buffers mode is selected, the POS-PHY Level 4 MegaCore
function consists of the receiver processor logic, and a separate Atlantic FIFO buffer
for each port.
The advantage of the individual buffers mode is that each Atlantic interface can be
accessed in parallel and independently, and the MegaCore function handles the status
generation automatically. The disadvantage is that because the number of ports
directly increases the logic utilization, the individual buffers mode is not well suited
for applications with a large number of ports.
A major component of a SPI-4.2 system is flow control. Flow control is achieved by
periodically sending near-end FIFO buffer status to the far-end device’s scheduler
over the status channel.
Collectively, the status processor blocks calculate, format, and transmit the status
channel.
Starting at the physical interface and working back to the FIFO buffers, the flow
control has the following operation.
The status PHY block (rx_stat_phy) generates rsclk given some reference clock:
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In 128-bit variations, the rsclk runs at the rdint_clk rate.
In 64-bit variations, the rsclk runs at 1/2 the rdint_clk rate.
In 32-bit variations, the rsclk runs at 1/4 of the rdint_clk rate.
POS-PHY Level 4 MegaCore Function User Guide
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