IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 33

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 3: Parameter Settings
Optional Features
December 2010 Altera Corporation
Each FIFO RAM block is implemented independently in the available device memory
(for example, with M512, M4K, or M9K blocks) and each device memory has a fixed
number of available configurations. The FIFO RAM block depth for small buffer
configurations (such as 128 × 36 of M4K memory) can be smaller than the minimum
configurable depth of the memory element, meaning that the remainder of the
memory is wasted. By using 2 FIFO RAM blocks instead of 4 you may get better
memory utilization.
Figure 3–3. Comparison of FIFO RAM Blocks
Both FIFO buffer width and FIFO buffer size affect memory utilization. The
improvement for a two block FIFO buffer configuration versus a four block FIFO
buffer configuration ranges from half the memory consumption for small buffers, to
the same memory consumption for large buffers.
Table 3–5
FIFO RAM blocks versus 2 FIFO RAM blocks.
Table 3–5. Memory Utilization Comparison
Note to
(1) Stratix II device, receive (Rx), shared buffer, data path width 32, parity enabled.
(bytes)
Buffer
1,024
2,048
4,096
8,192
Size
512
Table
gives a comparison of the memory utilization for a Stratix II device with 4
2 FIFO RAM Blocks 4 FIFO RAM Blocks 2 FIFO RAM Blocks
4 M4K
4 M4K
6 M4K
12 M4K
24 M4K
3–5:
4 FIFO RAM Blocks
2 FIFO RAM Blocks
Atlantic Interface Width 32
Figure 3–3
Write Side
Write Side
4 M4K + 4 M512
8 M4K
8 M4K
12 M4K
24 M4K
shows the comparison of FIFO RAM blocks.
(size = fifo_size/4)
(size = fifo_size/4)
(size = fifo_size/4)
(size = fifo_size/2)
(size = fifo_size/4)
(size = fifo_size/2)
FIFO Block 1
FIFO Block 2
FIFO Block 3
FIFO Block 1
FIFO Block 0
FIFO Block 0
(Note 1)
4 M4K + 2 M512
6 M4K
6 M4K
10 M4K
20 M4K
POS-PHY Level 4 MegaCore Function User Guide
Atlantic Interface Width 64
Read Side
Read Side
8 M4K + 4 M512
12 M4K
20 M4K
8 M4K + 4 M512
12 M4K
4 FIFO RAM Blocks
3–11