IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 25

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 3: Parameter Settings
Basic Parameters
December 2010 Altera Corporation
LVDS Data Rate
PLL Input Frequency
Data Path Width
Buffer Mode
f
1
1
For a transmitter, the LVDS data rate specifies the data rate out of the FPGA, on each
LVDS pair.
IP Toolbench uses this parameter to instantiate and configure the ALTLVDS
megafunction that includes the fast PLL. For example, to configure a transmitter with
a data rate of 700 Mbps on the tdat line, enter 700 in the LVDS Data Rate field of IP
Toolbench. This rate corresponds to a 350 MHz DDR clock on tdclk.
For a receiver, the LVDS data rate specifies the data rate into the FPGA, on each LVDS
pair, and sets the phase-locked loop (PLL) clock rate.
IP Toolbench uses the LVDS data rate to instantiate and parameterize the ALTLVDS
megafunction that includes the fast PLL. For example, for a receiver with a data rate
of 700 Mbps on each rdat line, enter 700 in LVDS data rate. This value corresponds to
a 350 MHz double-data rate (DDR) clock on rdclk.
For a transmitter only, you can enter the PLL input frequency. To enter the PLL
frequency, you must click Import PLL Frequency, to open the ALTLVDS wizard and
view the available input PLL frequencies.
When you change the data path width, the PLL input frequency changes.
Do not type the PLL frequency into the box.
The Data path width affects two important aspects of the MegaCore function: size
and performance. The MegaCore function offers the following options:
■
■
■
For approximate resource usage and performance of example POS-PHY Level 4
variations, refer to
The POS-PHY Level 4 MegaCore function supports the following two buffer modes:
■
■
With Shared buffer with embedded addressing, all ports share a single Atlantic
buffer with an 8-bit address field that supports up to 256 ports. The data is read from
the Atlantic buffer in the same order as it is received. The shared buffer with
embedded addressing mode is smaller than the individual buffers mode, and allows
you to develop your own buffering and status generation implementation.
128 bits running at a frequency of 1/8 the LVDS data rate
64 bits running at 1/4 the LVDS data rate
32 bits (quarter rate) running at 1/2 the LVDS data rate (for non-standard
applications at a maximum of 250 Mbps)
Shared buffer with embedded addressing
Individual buffers
“Performance and Resource Utilization” on page
POS-PHY Level 4 MegaCore Function User Guide
1–6.
3–3