IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 71

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description—Receiver
Latency Information
Latency Information
December 2010 Altera Corporation
The receiver MegaCore functions involve two kinds of latency: data latency and
status transmit latency.
Data latency is defined as the latency from the SPI-4.2 LVDS receive pins to the
internal Atlantic interface that is writing into the buffer(s). For the shared buffer with
embedded addressing mode, it does not include the time the data spends in the
buffer.
Status transmit latency is the number of clock cycles from when the status is provided
from the user logic or the Atlantic buffer until it is transmitted to the adjacent device,
assuming that the status channel is not disabled. It does not include the latency
involved in waiting for the previous transmit message to complete, or in waiting for
the status for other ports to be sent.
Figure 4–14 on page 4–31
receiver finish gives the receiver L
mode.
Figure 4–14. L
18
3
MAX
SPI-4.2
Individual Buffers Mode Overview
Receiver MegaCore Function
shows a picture of the L
CTL Word Processor)
Transmit
Receiver Processor
Status
(ALTLVDS, DPA,
Atlantic Buffer,
MAX
Data Latency
) for a receiver using the individual buffers
Generator
Status
& Port
Table
Status Latency
MAX
POS-PHY Level 4 MegaCore Function User Guide
FPGA
contributions (receiver start to
Processor
Buffer N
Buffer 1
Buffer 2
Status
4–31