IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 120

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

C–2
POS-PHY Level 4 MegaCore Function User Guide
The required frequency from restriction (b) is:
If you increase the LVDS data rate to 820 Mbps (rdint_clk = rsclk = 102.5 MHz), the
new minimum required rxsys_clk frequency from restriction (a) is:
and from restriction (b) is:
If you do not want to increase the rxsys_clk frequency, you can increase the status
frame length. By setting the calendar multiple to 2, the required frequency from
restriction (b) is
By changing the calendar multiple to 2, the required minimum rxsys_clk frequency
is 131.2 MHz (from restriction (a)).
Figure C–1. Minimum Frequency Ratio versus Packet Size
Status Frame Length = 3
rxsys_clk frequency ≥ 100 × (3+1) /3 = 100 × 4/3 = 133.34 MHz
For this example, rxsys_clk ≥ 133.34 MHz
(4/3.125) × 102.5 = 131.2 MHz
102.5 × 4/3 = 136.667 MHz
Status frame length = 4
rxsys_clk frequency ≥ 102.5 × 5/4 = 128.125 MHz
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
Ratio
20
30
MegaCore Width = 64
MegaCore Width = 128
40
50
60
70
80
90
Appendix C: Optimum Frequency for rxsys_clk
100 110
December 2010 Altera Corporation
Packet Size
(Bytes)