IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 9

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 1: About This MegaCore Function
General Description
General Description
December 2010 Altera Corporation
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The packet over SONET/SDH physical layer (POS-PHY) Level 4 interface, first
developed by the SATURN
Internetworking Forum (OIF) as the System Packet Interface Level 4—Phase 2 (SPI-
4.2). Therefore, POS-PHY Level 4 and SPI-4.2 are synonymous.
The POS-PHY Level 4 MegaCore function uses the SPI-4.2 interface for high-speed
cell and packet transfers between physical (PHY) and link-layer devices. The SPI-4.2
interface supports a data width of 16 bits (LVDS solution) and can be a PHY-link, link-
link, link-PHY, or PHY-PHY connection in multi-gigabit applications, including:
asynchronous transfer mode (ATM) and packet over SONET/SDH (STS-192/STM-
64), 10 Gigabit Ethernet, and multi-channel Gigabit and Fast Ethernet.
In compliance with the SPI-4.2 interface specification, the POS-PHY Level 4 MegaCore
function allows you to implement transmit and receive functions.
Configurable data path width—affecting the MegaCore function size and speed—
for various performance requirements and applications:
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Supports up to 256 ports
Fixed start of packet (SOP) alignment to the most significant byte lane eases
subsequent packet processing
First-in first-out (FIFO) buffer status management and indications
Configurable FIFO buffer modes
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Error detection and handling
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IP functional simulation models for use in Altera-supported VHDL and Verilog
HDL simulators
I-Tested certification
128 bits
64 bits
32 bits (quarter rate)
Shared buffer with embedded addressing
Individual buffers
Protocol checking—SPI-4.2 datapath state machine check and repair
Atlantic FIFO buffer overflow handling
Status framing hysteresis (good and bad thresholds)
DIP-4 hysteresis (good and bad thresholds)
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Development Group, was adopted by the Optical
POS-PHY Level 4 MegaCore Function User Guide
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