IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 98

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

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Latency Information
POS-PHY Level 4 MegaCore Function User Guide
The transmitter MegaCore functions involve two kinds of latency: data latency and
status receive latency.
Data latency is defined as the latency from the Atlantic interface that is reading from
the buffer to the SPI-4.2 LVDS transmit pins. It does not include the latency through
the buffer. For external status, the numbers assume that the aN_atxclk is faster than
the tsclk thus ensuring that the clock-crossing FIFO buffer is empty.
Status receive latency is defined as the latency from the point at which the last cycle of
a valid status message is received (the DIP-2 error code) to the point at which the user
logic or the transmit scheduler can use the status information. It does not include the
time spent waiting for a complete, error-free status message.
Figure 5–12
transmitter finish gives the transmitter L
Figure 5–12. L
shows a generic picture of the L
MAX
Top Level Overview
MAX
MAX
).
contributions (transmitter start to
Chapter 5: Functional Description—Transmitter
December 2010 Altera Corporation
Latency Information