IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 93

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 5: Functional Description—Transmitter
Signals
Table 5–7. SPI-4.2 Status Channel Control and Status (Part 3 of 3)
December 2010 Altera Corporation
err_ts_frm
err_ts_dip2
ctl_ts_callen[7:0]
ctl_ts_calm[7:0]
stat_ts_calsel
tav_clk
tav_address[3:0]
tav_chipselect
tav_write
tav_read
tav_writedata[15:0]
tav_readdata[15:0]
tav_waitrequest
Signal
Output
Output
Input
Input
Output
Input
Input
Input
Input
Input
Input
Output
Output
Direction
tsclk
tav_clk
tav_clk
Clock Domain
Indicates the frame was malformed. Possible causes
are:
■
■
■
Asserted synchronous to stat_ts_dip2state.
Indicates the calculated DIP-2 did not match the DIP-
2 word in the status frame. Asserted synchronous to
stat_ts_dip2state.
Sets the expected length of the calendar in the status
frame. This port is absent if Asymmetric Port
Support is turned on. Only change at reset, or when
ctl_ts_rsfrm and stat_ts_disabled are both
asserted.
Sets the expected number of status calendar
repetitions between framing and DIP-2 in the status
frame. This port is absent if Asymmetric Port
Support is turned on. Only change at reset, or when
ctl_ts_rsfrm and stat_ts_disabled are both
asserted.
Indicates the currently selected calendar when
Hitless B/W reprovisioning is turned on. Zero
indicates ‘b01, and one indicates ‘b10. It is set to
zero when Hitless B/W reprovisioning is turned off.
This port is absent if Asymmetric Port Support is
turned off.
Avalon-MM clock. Signals prefixed by tav_ are
synchronous to this clock. This port is absent if
Asymmetric Port Support is turned off.
Avalon-MM address. This port is absent if
Asymmetric Port Support is turned off.
Avalon-MM chip select. This port is absent if
Asymmetric Port Support is turned off.
Avalon-MM write enable. This port is absent if
Asymmetric Port Support is turned off.
Avalon-MM read enable. This port is absent if
Asymmetric Port Support is turned off.
Avalon-MM write data. This port is absent if
Asymmetric Port Support is turned off.
Avalon-MM read data. This port is absent if
Asymmetric Port Support is turned off.
Avalon-MM wait request. This port is absent if
Asymmetric Port Support is turned off.
Calendar did not begin with a framing word.
Hitless bandwidth repositioning is turned on, and
calendar select word was not ‘b01 or ‘b10.
Unexpected framing word was in the calendar
portion of the frame.
POS-PHY Level 4 MegaCore Function User Guide
Description
5–21