IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 135

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Introduction
Receiver Signals
December 2010 Altera Corporation
1
The POS-PHY Level 4 MegaCore
replaceable functions for earlier versions. The clocking structure of version 2.4.x and
2.3.x have been modified to allow the Atlantic
either a single clock domain, or multiple clock domains. As a result, the clock signal
names and the signals naming conventions have changed. Some of the control and
status signals are now synchronous to a different clock domain.
The restrictions outlined in
structure to operate properly.
The POS-PHY Level 4 MegaCore function version 2.4.x and 2.3.x also provide support
for asymmetric ports and hitless bandwidth reprovisioning. When Asymmetric ports
support is turned on, an Avalon
instantiated in the MegaCore function. The signals associated with the Avalon-MM
interface were not available in previous versions of the MegaCore function.
In the 2.2.x versions of the MegaCore function, the logic was located in the reference
clock (rrefclk) domain. Writing to the Atlantic FIFO buffer also occurred in the
rrefclk domain. The rrefclk was derived from rdclk (SPI-4.2 receive clock). Signals
synchronous to rrefclk were infixed by _rr_. Reading from the Atlantic FIFO buffer
was done using the Atlantic clock (aN_arxclk).
In the 2.4.x and 2.3.x versions of the MegaCore function, rrefclk has been renamed
rdint_clk. Signals synchronous to rdint_clk are infixed by _rd_. Only part of the
function is synchronous to rdint_clk; the bulk of the function is synchronous to
rxsys_clk. The rxsys_clk clock is an input to the MegaCore function, and signals
synchronous to this clock are infixed by _ry_. In 32-bit data path, and shared buffer
with embedded addressing variations, the rxsys_clk is not input and is internally
assigned rdint_clk. The signals remain infixed by _ry_, and the clock domain is still
referred to as rxsys_clk.
In the single clock domain mode, rxsys_clk writes to the Atlantic FIFO buffer. In the
multiple clock domain mode, reading from the Atlantic FIFO buffer is done using the
Atlantic clock (aN_arxclk). For more information, refer to the
section of the
“Functional Description—Receiver”
Table C–1 on page C–1
®
®
Memory-Mapped (Avalon-MM) interface is
function version 2.4.x and 2.3.x are not drop-in
G. Conversion from v2.2.x
™
first-in first-out (FIFO) buffers to use
chapter.
POS-PHY Level 4 MegaCore Function User Guide
must be followed for the clocking
“Clock Structure”