IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 90

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

5–18
Table 5–5. Atlantic Transmit Interface (Slave Sink)
POS-PHY Level 4 MegaCore Function User Guide
aN_atxclk
aN_atxdav
aN_atxena
aN_atxdat[?:0]
aN_atxsop
aN_atxeop
aN_atxmty[?:0]
aN_atxerr
aN_atxadr[7:0]
Note to
(1) N is equal to the number of ports for the individual buffers mode; N is equal to zero when you turn on Shared Buffer with Embedded
Addressing.
Table
Signal
5–5:
Input
Output
Input
Input
Input
Input
Input
Input
Input
Direction
aN_atxclk
Domain
Clock
Atlantic Clock (one for each Atlantic interface). This input is absent
and internally connected to tdint_clk if a single clock domain is
selected. Signals prefixed with aN_ are synchronous to this clock.
Atlantic data available (one for each Atlantic interface). Asserted when
the Atlantic FIFO buffer has at least ctl_atx_fth bytes of free space
available.
Atlantic enable (one for each Atlantic interface).
Atlantic data bus (one for each Atlantic interface). The width is set by
the Atlantic interface width parameter.
Atlantic start of packet (one for each Atlantic interface).
Atlantic end of packet (one for each Atlantic interface).
Atlantic empty signal (one for each Atlantic interface). Number of
invalid octets on the lower bits of aN_atxdat. Valid only when
aN_atxeop is asserted, must be zero otherwise. The width is
log2(Atlantic interface width/8).
Atlantic Error (one for each Atlantic interface). Translates to an EOP-
Abort on the transmit data bus.
Atlantic port address. Only present when you turn on turn on Shared
Buffer with Embedded Addressing.
(Note 1)
Chapter 5: Functional Description—Transmitter
Description
December 2010 Altera Corporation
Signals