IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 89

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 5: Functional Description—Transmitter
Signals
Table 5–3. SPI-4.2 Transmit Interface
Table 5–4. Global
December 2010 Altera Corporation
tdclk
tctl
tdat[15:0]
tsclk
tstat[1:0]
trefclk
tdint_clk
txsys_clk
txreset_n
txinfo_aot[12:0]
stat_tx_pll_locked
ctl_tx_pll_areset
Signal
Signal
Output
Output
Output
Input
Input
Direction
Input
Output
Input
Input
Output
Output
Input
Direction
tdclk
tsclk
tsclk
(either edge)
Domain
Clock
trefclk
tdint_clk
txsys_clk
Asynchronous
Static
Asynchronous
Clock Domain
SPI-4.2 differential transmit clock. Double-data rate clock
synchronous to tctl and tdat.
SPI-4.2 differential transmit control. When set to logic 1, the word
on tdat is a control word. When set to logic 0, the word on tdat
is a payload word.
SPI-4.2 differential transmit data bus. Bus carries packet/cell
payload or in-band control words.
SPI-4.2 transmit status clock. All signals infixed by _ts_ are
synchronous to this clock.
SPI-4.2 transmit status channel. Indicate the downstream device’s
FIFO buffers fill levels to the upstream device’s scheduler.
Transmitter reference clock. Typically route to LVDS PLL.
Signals infixed by _tr_ are synchronous to this clock.
Derived from trefclk. Signals infixed by _td_ are
synchronous to this clock.
System clock. Signals infixed by _ty_ are synchronous to
this clock.
Active low asynchronous reset to all internal logic, including
Atlantic FIFO buffers. Refer to
page
Fixed output information signal that contains the value for the
current AOT number for the release.
Locked signal directly from fast PLL in ALTLVDS for full rate
variations. Absent in quarter-rate variations.
Asynchronous reset signal directly to fast PLL in ALTLVDS for
full-rate variations. Absent in quarter-rate variations.
5–11.
.
POS-PHY Level 4 MegaCore Function User Guide
Description
Description
“Reset Structure” on
5–17