IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 122

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

D–2
POS-PHY Level 4 MegaCore Function User Guide
Probe Points
1
Altera recommends that you make some of the POS-PHY Level 4 MegaCore
pins and status signals available for probing using test points or connectors for logic
analyzers. Good debug connectors take little space on a PCB and have a minimal
effect on signal integrity (for example, Samtec ASP65067-01 connectors).
Receiver MegaCore Functions
The following signals connected to the POS-PHY Level 4 receiver MegaCore functions
should be made available for debugging:
■
■
■
In addition to these receiver signals, it may be useful to provide test points for similar
debug and status signals from the adjacent device.
Transmitter MegaCore Functions
The following signals connected to the POS-PHY Level 4 transmitter MegaCore
functions should be made available for debugging:
SPI-4.2 Data Interface
■
■
■
SPI-4.2 data interface signals:
■
■
■
SPI-4.2 status interface signals:
■
■
Other useful debug signals:
■
■
■
■
■
■
■
■
■
■
tdat[15:0]
tctl
tdclk
rdat[15:0]
rctl
rdclk
rstat[1:0]
rsclk
FPGA reset
stat_rd_dpa_locked
stat_rd_dpa_lvds_locked
err_rd_dip4
err_ry_msopN
err_ry_meopN
rdint_clk
aN_arxerr
aN_arxeop
aN_arxclk
December 2010 Altera Corporation
Appendix D: Board Design
Design for Testability
®
function