IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 37

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 3: Parameter Settings
Protocol Parameters
December 2010 Altera Corporation
If MaxT = 0, periodic training patterns are disabled. If the transmitter status framer is
out of synchronization, the transmitter sends continuous training patterns regardless
of the MaxT parameter. Training patterns always begin on the rising edge of the clock
(tdclk).
For the Training pattern repetition value, the training sequence includes one IDLE
word, plus ALPHA(a) × 20 training words. ALPHA is a user-selectable option (0 to 255).
Zero (0) is equal to 256 training pattern repetitions.
The training sequence includes one IDLE control word, plus a × 20 words. The twenty
words are separated into ten consecutive tdat words of 16’h0FFF with tctl of 1’b1,
followed by ten consecutive tdat words of 16’hF000 with tctl of 1’b0.
For the Status sync good and Status sync bad threshold values, two 4-bit inputs,
good_level (ctl_ts_sync_good_theshold) and bad_level
(ctl_ts_sync_bad_theshold), are associated with the stat_ts_sync signal.
The stat_ts_sync signal is asserted high when a good_level number of consecutive
status frames are received without frame or DIP-2 errors. The stat_ts_sync signal is
deasserted when a bad_level number of DIP-2 errors or frame errors have been
received since the last error-free frame.
The FIFO buffer threshold high (FTH) for transmitter variations controls when the
aN_atxdav signal is asserted and deasserted for the write side of the FIFO buffer. The
aN_atxdav signal indicates when there is room available to write new data into the
FIFO buffer, and is asserted whenever the remaining space in the buffer is greater than
the FTH value.
This threshold is defined in terms of bytes, with a valid range from N to buffer size
bytes, in N-byte increments, where:
■
■
■
The N-byte values depend on the Atlantic interface width and on the Lite transmitter
setting.
Table 3–6. N-Byte Values
N = 4 or 8 bytes for 32-bit data path variations
N = 8 or 16 bytes for 64-bit data path variations
N = 16 or 32 bytes for 128-bit data path variations
Datapath Width
Table 3–6
128
32
64
shows the N-byte values, based on the transmitter's settings.
Atlantic Interface
Width
128
128
32
64
64
Lite Transmitter
On or off
POS-PHY Level 4 MegaCore Function User Guide
Off
Off
On
On
—
—
N Bytes (FTH
Increment)
16
16
16
32
4
8
8
3–15