IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 67

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description—Receiver
Signals
Table 4–9. SPI-4.2 Channel Control and Status (Part 2 of 3)
December 2010 Altera Corporation
ctl_ry_rsfrm
ctl_ry_dip2err_ins
stat_ry_disabled
stat_ry_dip2state
err_ry_stat_fifo
ctl_ry_callen[7:0]
ctl_ry_calm[7:0]
stat_ry_calsel
Signal
Input
Input
Output
Output
Output
Input
Input
Output
Direction Clock Domain
rxsys_clk
When asserted, the ctl_ry_rsfrm signal forces the
receiver status channel into framing mode beginning at
the end of the next frame. You can use ctl_ry_rsfrm
to indicate that the receiver requires retraining.
If you assert ctl_ry_dip2err_ins while it is
calculating the DIP2, it inverts it. It does not invert the
statuses on the way and does not wait for the end of the
calendar to do the inversion. Also, if the error is set for
the calendar length (plus 2 cycles, 1 for DIP2 one for
FRM), it is only active on one DIP2 calculation.
Therefore you should not see two consecutive DIP2
errors.
Indicates that the calendar state machine is disabled,
and is transmitting continuous framing.
Indicates that the calendar state machine is in DIP-2
state.
Indicates that the status FIFO buffer has underflowed or
overflowed causing the status finite state machine to go
into continuous framing state (refer to
Mode” on page
underflows or overflows, ensure the clock relationships
meet Altera guidelines.
Sets the length of the calendar in the outgoing status
frame. Zero is interpreted as 256. This port is absent if
asymmetric port support is turned on. Only change at
reset, or when ctl_ry_rsfrm and
stat_ry_disabled are both asserted.
Sets the number of status calendar repetitions between
framing and DIP-2 in the outgoing status frame. If
err_ry_stat_fifo is asserted, you need to increase
the number of repetitions. Refer to
on page
absent if asymmetric port support is turned on. Only
change at reset, or when ctl_ry_rsfrm and
stat_ry_disabled are both asserted.
Indicates the currently selected calendar when hitless
bandwidth reprovisioning is enabled. It is set to zero
otherwise. This port is absent if asymmetric port
support is turned off.
4–10. Zero is interpreted as 256. This port is
POS-PHY Level 4 MegaCore Function User Guide
4–10). If the status FIFO buffer regularly
Description
“Single Clock Mode”
“Single Clock
4–27