IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 117

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

December 2010 Altera Corporation
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1
This appendix explains how to share a PLL between one receiver and one transmitter
POS-PHY 4 MegaCore functions and between two transmitter cores.
Figure B–1
you share a PLL between a receiver and transmitter core.
Even though
instance as if it is one PLL.
Figure B–1. Connect rdclk and trefclk Signals
To share the PLL, follow these steps:
The LVDS data rates must be the same for each core.
1. Create a new Quartus II project, but call the project name and the top-level entity
2. Create your receiver core.
3. Create your transmitter core.
names different names.
trefclk
reset
reset
tdclk
rdclk
shows how to connect the reset and the rdclk and trefclk signals when
Figure B–1
<variation name>_rx_core.v
<variation name>_tx_core.v
altlvds Megafunction
altlvds Megafunction
Separate PLLs
<variation name>.v
<variation name>.v
Top-Level Entity
PLL
PLL
shows two PLLs, the Quartus II software optimizes the PLL
B. Sharing PLLs for Multicore Designs
trefclk
reset
tdclk
rdclk
POS-PHY Level 4 MegaCore Function User Guide
reset
<variation name>_rx_core.v
<variation name>_tx_core.v
altlvds Megafunction
altlvds Megafunction
<variation name>.v
<variation name>.v
Shared PLL
Top-Level Entity
PLL
PLL