IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 82

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

5–10
Figure 5–4. Clock Layout Diagram (Full Rate)
Notes to
(1) Stratix and Stratix GX devices use trefclk for tdint_clk. All other device families use the PLL output clock.
(2) The single clock mode removes the separate Atlantic clocks.
(3) The embedded address mode has only one buffer; the individual buffers mode can have more than one buffer.
POS-PHY Level 4 MegaCore Function User Guide
Figure
5–4:
ctl_ts_statedge
Figure 5–4 on page 5–10
transmitter MegaCore function in full-rate mode.
Figure 5–5 on page 5–11
function, for 32-bit (quarter rate) SPI-4.2 mode variations. For 32-bit variations, the
ALTLVDS_TX block is replaced by an ALTDDIO_OUT block and there is no LVDS
PLL function that is clocked by trefclk.
tdat[15:0]
tstat[1:0]
trefclk
tsclk
tdclk
tctl
LVTTL
LVTTL
altlvds Megafunction
LVDS
PLL
SERDES
shows the clocking structure for the transmitter MegaCore
shows the multiple clock domain clocking structure for the
Processor
Data
tdint_clk
2
Processor
Atlantic
Buffer 0
Status
Chapter 5: Functional Description—Transmitter
December 2010 Altera Corporation
a0_atxclk
Atlantic
Interface 0
txsys_clk
Clock Structure