IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 64

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

4–24
Signals
Table 4–5. SPI-4.2 Receive Interface
Table 4–6. Global
POS-PHY Level 4 MegaCore Function User Guide
rdclk
rctl
rdat[15:0]
rsclk
rstat[1:0]
rdint_clk
rxsys_clk
rxreset_n
rxinfo_aot[12:0]
stat_rx_pll_locked
ctl_rx_pll_areset
Signal
Signal
LVDS Clock
Input
LVDS Input
LVDS Input
LVTTL Output
LVTTL Output
Table 4–5
function. The active low signals are suffixed by _n.
Direction
Output
Input
Input
Output
Output
Input
Direction
through
rdclk
rsclk
(rdint_clk)
Clock Domain
Table 4–11
rdint_clk
rxsys_clk
Asynchronous
Static
Asynchronous
Asynchronous
Clock Domain
list the I/O signals used in the receiver MegaCore
SPI-4.2 differential receive clock. Double-data rate clock
synchronous to rctl and rdat.
SPI-4.2 differential receive control.
When set to a logic 1, the word on rdat is a control word. When
set to a logic 0, the word on rdat is a payload word.
SPI-4.2 differential receive data bus. Bus carries packets/cells or
in-band control words.
SPI-4.2 receive status clock. This signal uses a regular LVTTL
data pin instead of a dedicated output clock pin. Derived from
rdclk. Active if rdclk is active.
SPI-4.2 receive status channel. Indicates the downstream
device’s FIFO buffers’ fill level to the upstream device’s scheduler.
Derived from rdclk. Signals infixed with _rd_ are
synchronous to this clock. Active if rdclk is active.
System clock. Signals infixed with _ry_ are synchronous to
this clock.
Active low asynchronous reset to all internal logic, including
Atlantic FIFO buffers. Refer to
page
Fixed output information signal that contains the current
AOT number for the release.
Locked signal directly from fast PLL in ALTVDS for full rate
variations, or enhanced PLL in quarter-rate variations.
Asynchronous reset signal directly to fast PLL in ALTVDS for
full rate variations, or enhanced PLL in quarter-rate
variations.
4–12.
Chapter 4: Functional Description—Receiver
Description
Description
“Reset Structure” on
December 2010 Altera Corporation
Signals