IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 66

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

4–26
Table 4–8. Atlantic FIFO Buffer Control and Status (Part 2 of 2)
Table 4–9. SPI-4.2 Channel Control and Status (Part 1 of 3)
POS-PHY Level 4 MegaCore Function User Guide
err_ry_fifo_oflwN
ctl_ry_errchk_chkpkt
err_ry_msopN
err_ry_meopN
stat_ry_mp_erradr[7:0]
Note to
(1) For 128-and 64-bit variations, N is equal to log2(buffer size /(data path width × 16). For 32-bit variations, N is equal to log2(buffer size/data
ctl_ry_ae[n:0]
ctl_ry_af[n:0]
ctl_ry_fifostatoverride
ctl_ry_extstat_val
ctl_ry_extstat_adr[7:0]
ctl_ry_extstat[1:0]
ctl_rs_statedge
Note to
(1) The external status address you provide does not have to be incrementing or have any set sequence. You can provide any address value, at any
path width×8).
time. If the external address provided is for an unprovisioned port, the value is written into the internal RAM at that address, but the internal
status block never reads from that location.
Table
Table
4–8:
4–9:
Signal
Signal
(1)
(1)
(1)
Output
Input –
Static
reset
Output
Output
Output
Direction Clock Domain
Input
Input
Input -
Static
Input
Input
Input
Input -
Static
constant
Direction Clock Domain
rxsys_clk
rxsys_clk
rsclk
Indicates that the FIFO buffer has overflowed, and data has
been lost (one for each Atlantic interface).
Atlantic FIFO error checking enable. Disable to ignore
missing SOP and missing EOP detection and correction.
Value applies to all Atlantic buffer levels. Only change at
reset.
Indicates a packet was received on the SPI-4.2 bus with a
missing start of packet (one for each Atlantic buffer).
Indicates a packet was received on the SPI-4.2 bus with a
missing end of packet (one for each Atlantic buffer).
Address qualifier for err_ry_meop and err_ry_msop
flags. Only present for the shared buffer with embedded
addressing mode.
Almost empty defines starving to hungry threshold.
Units are in bytes. Value applies to all Atlantic buffers.
Only change at reset.
Almost full defines hungry to satisfied threshold. Units
are in bytes. Value applies to all Atlantic buffers. Only
change at reset.
Asserting this signal allows external logic to control the
outgoing status of each port. Only change at reset.
Valid qualifier for the external status input. This value is
ignored if ctl_ry_fifostatoverride is deasserted.
Port number for the external status value. This value is
ignored if ctl_ry_fifostatoverride is deasserted.
Status for port indicated by ctl_ry_extstat_adr.
This value is ignored if ctl_ry_fifostatoverride is
deasserted.
Controls the edge of rsclk on which transitions of
rstat occur. (1 = positive edge, 0 = negative edge).
Only change at reset.
Chapter 4: Functional Description—Receiver
Description
Description
December 2010 Altera Corporation
Signals