IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 52

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

4–12
Figure 4–5. Clock Layout Diagram (Quarter Rate)
Notes to
(1) rxsys_clk is internally connected to rdint_clk in 32-bit shared buffer with embedded addressing mode variations.
(2) The single clock mode removes the separate Atlantic clocks.
(3) The embedded address mode has only one buffer; the individual buffers mode can have more than one buffer.
(4) In 32-bit (quarter-rate) SPI-4.2 mode, this PLL only provides a phase shift for the incoming rdclk.
Reset Structure
POS-PHY Level 4 MegaCore Function User Guide
Figure
Requirements for rxsys_clk
4–5:
f
stat_rx_pll_locked
ctl_rx_pll_areset
the SPI-4.2 data rate is 200 Mbps. Most of the quarter-rate receiver MegaCore function
runs off rdint_clk, including all data path processors and the write side of the FIFO
buffer.
function, for 32-bit (quarter-rate mode) variations that use the ALTDDIO_IN
megafunction.
The MegaCore function’s protocol logic and all Atlantic FIFO buffers share a common
clock called rxsys_clk that clocks both the write and optionally the read side of the
Atlantic FIFO buffers.
Table 4–2
Table 4–2. Frequency Guidelines—rxsys_clk
For detail on the optimum setting of rxsys_clk, refer to
Frequency for
By default, the rxreset_n signal is the asynchronous global reset for the MegaCore
function. It is internally metastable hardened and passed to each of the individual
clock domains.
rdat[15:0]
rstat[1:0]
Data Path Width
rdclk
rsclk
rctl
Figure 4–5
(Bits)
128
32
64
shows guidelines for the frequency of rxsys_clk.
rxsys_clk.
ALTDDIO_OUT
shows the clocking structure used by the receiver MegaCore
(Note 4)
ALTDDIO_IN
EPLL
rdint_clk
2
Processor
Processor
Status
Data
Worst Case Frequency Requirement
1.25 × rdint_clk
1.0 × rdint_clk
1.6 × rdint_clk
Buffer N
Atlantic
Buffer 0
Atlantic
Chapter 4: Functional Description—Receiver
Chapter C, Optimum
December 2010 Altera Corporation
rxsys_clk
(Note 1)
a0_arxclk
Atlantic
Interface 0
aN_arxclk
(Note 2, 3)
Atlantic
Interface N
Reset Structure