IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 103

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 6: Testbench
Receiver Testbench Examples
Table 6–2. Function Format
Receiver Testbench Examples
December 2010 Altera Corporation
Training
pattern
Idle
Data packet
Command
spi_gen.tp (width, number)
spi_gen.idles (number)
spi_gen.pkt (port_number,
err, size, num)
There are three pattern generation functions capable of generating idles, training
patterns, and data packets.
All of the packets are sent in sequence with no breaks between them. However, idles
can be inserted by adding the idle command in the testbench data generation section.
After all packets have been sent, the idle pattern is repeated until the end of the
simulation.
The testbench concludes by checking that all of the packets have been received. In
addition, it checks that the Atlantic packet receivers (data analyzer modules, one for
each port) have not detected any errors in the received packets. If no errors have been
detected, and all packets have been received, the testbench issues a message stating
that the simulation is successful.
If errors have been detected, a message states that the testbench has failed. If not all
packets have been detected, a message states that the testbench is incomplete. The
tb.exp_chk_cnt variable determines the number of checks done to ensure
completeness of the testbench. For each port tested, one completeness check is done.
In addition, a final check is done for the conclusion of the testbench.
Optionally, the testbench can create backpressure on the SPI-4.2 interface. When the
backpressure variable is defined, backpressure is generated on one or more ports by
first turning off the data analyzer receiver for the appropriate port. As the receive
FIFO buffer begins to fill, it goes from the hungry state to the satisfied state. When the
FIFO buffer is satisfied, the status on the SPI-4.2 interface notifies the packet
generation module to stop sending data. There is a break in packet generation during
which idles are sent. After the status returns to the hungry state, the packet generation
resumes.
In addition to the tasks described in
module also has the following four tasks, which you can use to generate error signals
when running the testbench:
■
■
■
■
Table 6–3
pkt2
task_cw
task_cw2
task_pay
Format
describes the four error generation tasks in more detail.
width is the number of clock cycles the training pattern takes;
number is the number of training pattern sequences.
number is the number of sequential idles
port_number is the target port for the packet. err is set to zero;
size is the packet size in bytes (2-2
sequence number.
Table 6–2
Table 6–2 on page
shows the format of each function.
Description
POS-PHY Level 4 MegaCore Function User Guide
6–3, the packet generation
16
bytes); num is the packet
6–3