IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 11

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 1: About This MegaCore Function
MegaCore Verification
MegaCore Verification
December 2010 Altera Corporation
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For further information on this interface, refer to the System Packet Interface Level 4
(SPI-4) Phase 2 Revision 1: OC-192 System Interface for Physical and Link Layer Devices,
available at www.oiforum.com.
Atlantic Interface
The Atlantic interface is an Altera-developed synchronous protocol supporting both
packets and cells. The POS-PHY Level 4 MegaCore function is an Atlantic interface
slave that transfers packets to or from the user-side logic. The Atlantic interface
provides a connection between the FIFO buffer and user logic.
For further information on this interface, refer to the
Specification.
Avalon-MM Interface
The Altera Avalon-MM interface is a simple bus architecture that connects on-chip
processors (or external processor interfaces) and peripherals. The Avalon-MM
interface specifies the port connections between master and slave components, and
specifies the timing by which these components communicate.
All Avalon-MM signals are synchronized to the Avalon-MM clock (rav_clk/tav_clk).
This synchronization simplifies the relevant timing behavior of the Avalon-MM
interface and facilitates integration with high-speed peripherals.
In this version of the POS-PHY Level 4 MegaCore function, the Avalon-MM module is
a discrete unit that is instantiated by the MegaWizard
Port Support is turned on.
For further information on this interface, refer to the
The POS-PHY Level 4 MegaCore function has been rigorously tested and verified in
hardware for different platforms and environments. Each environment has individual
test suites that are designed to cover the following five categories of testability:
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These test suites contain several testbenches that are grouped and focused on testing
specific features of the POS-PHY Level 4 MegaCore function. These individual
testbenches set unique parameters for each specific feature test.
Results of the hardware verification tests are gathered in I-tested reports available for
different ASSP devices. For example, SPI-4.2 Interoperability with PMC-Sierra’s S/UNI
9953 and SPI-4.2 Interoperability with PMC-Sierra’s S/UNI 10×GE (PM3388).
For these reports, contact your local Altera sales representative or FAE.
Sanity
Flow Control
Error Management
Performance
Stress
POS-PHY Level 4 MegaCore Function User Guide
Atlantic Interface Functional
Avalon Interface
®
Plug-In, when Asymmetric
Specifications.
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