IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 76

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

5–4
POS-PHY Level 4 MegaCore Function User Guide
Data Processor (tx_data_proc)
1
Whenever a port is not selected, or exhausts its credit-counter register, the contents of
the next-credits holding register are loaded into the credit-counter register, and the
next-credits register is cleared. The next-credits register remains at zero until the next
status update is received.
As data is transmitted for a selected port, the credit-counter register is decreased. If
the credit counter ever has insufficient credits for an entire burst unit size transfer, the
scheduler switches to another port. This port cannot send again until the credits-
counter register is reloaded with the contents of the next-credits holding register.
Therefore, the MaxBurst1 and MaxBurst2 values must be greater than or equal to the
burst unit size value.
If the buffer runs out of data before the credit-counter register reaches zero, the
scheduler switches to another port. The leftover credits remain available until a new
status message causes the credit counter to be overwritten with fresh credits. The port
may be selected again before the next status update if the buffers fill again.
Both the next-credits and credits-counter tables are cleared when a loss of status sync
(LOSS) occurs, resuming to normal behavior when the LOSS is cleared.
The scheduler normally switches when the credits are exhausted or the port runs out
of data. If the scheduler switch on EOP feature is turned on, the scheduler also
switches to another port when an EOP is sent.
The data processor consists of two sub-blocks.
Atlantic Conversion
This block packs the data from the Atlantic interface into SPI-4.2 format.
Normally, this block enables data to be transferred from the transmit scheduler to the
Atlantic FIFO buffer. If ignore backpressure is disabled, a satisfied status for any port
causes the enable to drop at the next burst unit size boundary and data is not
transferred. This backpressure mechanism is described in
Embedded Addressing” on page
The MegaCore function cannot force insertion of control words except when the
address changes or there is insufficient data to send, regardless of the buffer type.
Control Word Insertion, DIP-4, and Training Pattern Insertion
This block inserts control words into the data path, and performs DIP-4 calculation
and insertion.
An EOP-abort condition can be generated on the SPI-4.2 interface by asserting
aN_atxerr with a valid aN_atxeop on the Atlantic interface. This condition is the only
one for which the EOP-abort bit is set in the transmitted control word.
This block also inserts the training pattern at the interval defined by the Maximum
Training Sequence Interval parameter (MaxT). If the status channel is receiving a
continuous framing pattern on the status channel, the MegaCore function sends
training patterns continuously.
5–2.
Chapter 5: Functional Description—Transmitter
“Shared Buffer with
December 2010 Altera Corporation
Block Description