IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 18

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

2–2
Table 2–1. Generated Files (Part 1 of 2)
POS-PHY Level 4 MegaCore Function User Guide
<variation name>_atlfifo_concat.v
<variation name>_dpa_concat.v
<variation
name>_pl4_rx_core_constraints.tcl
<variation name>_refresh_model.tcl
<variation name>_run_modelsim.tcl
<variation name>_rx_data_proc.ocp
<variation name>_rx_modules.v
<variation
name>_rx_data_phy_altlvds.v
<variation name>_rx_core.v
<variation name>_syn.v or
<variation name>_syn.vhd
f
c
File
For more information about the parameters, refer to
5. Click Step 2: Set Up Simulation in IP Toolbench.
You may only use these simulation model output files for simulation purposes and
expressly not for synthesis or any other purposes. Using these models for synthesis
creates a nonfunctional design.
6. Turn on Generate Simulation Model.
7. Choose the language in the Language list.
8. Some third-party synthesis tools can use a netlist that contains only the structure
9. Click OK.
10. Click Step 3: Generate in IP Toolbench.
An IP functional simulation model is a cycle-accurate VHDL or Verilog HDL
model produced by the Quartus II software.
of the MegaCore function, but not detailed logic, to optimize performance of the
design that contains the MegaCore function. If your synthesis tool supports this
feature, turn on Generate netlist.
Table 2–1
directory. The names and types of files specified in the IP Toolbench report vary
based on whether you created your design with VHDL or Verilog HDL
1
If you want to change your project from a receiver to a transmitter, delete all
the HDL files before you regenerate the MegaCore function.
describes the generated files and other files that may be in your project
An encrypted HDL file for Quartus II synthesis. This file is automatically added
to your Quartus II project. You should not modify this file.
A generated HDL file for Quartus II synthesis. This file is automatically added to
your Quartus II project. You should not modify this file.
Constraint settings file for Quartus II synthesis. Use this file to specify
constraints required to achieve performance requirements.
A Tcl script that regenerates the IP functional simulation model, in both Verilog
HDL (.vo) and VHDL (.vho) formats.
A Tcl script that automates the process of running the testbench with the IP
functional simulation model.
An OpenCore Plus file, for time limited or tethered hardware evaluation.
An encrypted HDL file for Quartus II synthesis. This file is automatically added
to your Quartus II project. You should not modify this file.
A generated HDL file for Quartus II synthesis. This file is automatically added to
your Quartus II project. You should not modify this file.
A generated HDL file for Quartus II synthesis. This file is automatically added to
your Quartus II project. You should not modify this file.
A timing and resource netlist for use in some third-party synthesis tools.
Description
Chapter 3, Parameter
December 2010 Altera Corporation
Chapter 2: Getting Started
Specify Parameters
Settings.