IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 75

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 5: Functional Description—Transmitter
Block Description
December 2010 Altera Corporation
Individual Buffers Transmit Scheduler (tx_sched)
f
1
1
When the ignore backpressure feature is turned on, the transmitter sends packets
whenever possible regardless of the incoming status channel. This mode assumes that
external logic is properly controlling the scheduling of ports, managing credits
(topping up to MaxBurst1 and MaxBurst2 as appropriate), and performing any other
related functions. Packets are sent whenever there are at least burst unit size bytes in
the Atlantic FIFO buffer, or an EOP.
When the ignore backpressure feature is turned off, the transmitter uses the status
channel to decide whether or not to transmit. Packets are only sent when none of the
ports in the incoming status channel are found to be satisfied, and there are at least
burst unit size bytes in the Atlantic FIFO buffer, or an EOP. With this mode, there is a
head-of-line blocking limitation, where if one port is satisfied it blocks all ports from
transmitting.
Regardless of the mode you select, the scheduling and insertion of the SPI-4.2 training
pattern is handled automatically by the MegaCore function.
In the shared buffer with embedded addressing mode, the MaxBurst1 and MaxBurst2
parameters are unused because the user logic does the scheduling.
Individual Buffers
When you turn on Individual Buffers, the POS-PHY Level 4 MegaCore function
consists of the transmitter processor logic, a credit-based round-robin scheduler, and a
separate Atlantic FIFO buffer for each port. Each buffer supports an optional Atlantic
error checking block.
The advantages of the individual buffers mode are the included scheduler, and that
each Atlantic interface can be accessed in parallel and independently. For individual
buffers transmitter variations, scheduling logic decodes the incoming status channel
and decides which buffer (port) to serve, and then reads from that buffer.
For more information, refer to
page
Because the number of ports directly increases the logic usage, the individual buffers
mode is not well suited for applications with a large number of ports.
For individual buffers variations, the transmit scheduler manages the SPI-4.2 per-port
credits, and transmits data from the appropriate FIFO buffer.
The scheduler includes a next-credit table that is updated when status is received, and
a second credit table that maintains the number of credits left. Each table has n port
entries, where each entry is henceforth referred to as a register.
The next-credits register contains the number of credits corresponding to the latest
status update. A starving status update loads the next-credit register with MaxBurst1.
A hungry status update loads the next-credit register with MaxBurst2. A satisfied
status update has no effect on the next-credits register.
5–3.
“Individual Buffers Transmit Scheduler (tx_sched)” on
POS-PHY Level 4 MegaCore Function User Guide
5–3