IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 45

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description—Receiver
Block Description
December 2010 Altera Corporation
Data Processor (rx_data_proc)
f
aligned, which can be detected by looking for the repeating training pattern. For every
align pulse, the ALTLVDS_RX megafunction sub-block shifts the data on the
corresponding channel by one bit, effectively in the serial domain. The actual shift
occurs in the serial domain for Stratix III and Stratix II devices, and in the parallel
domain for Stratix GX devices.
In Stratix III and Stratix II devices, the MegaCore function requires less than 220
training patterns (lock time) before it asserts the stat_rd_dpa_lvds_locked signal.
The err_rd_dpa signal is tied low.
In Stratix GX devices, the MegaCore function requires less than 700 training patterns
(lock time) before it asserts the stat_rd_dpa_locked signal. If alignment cannot be
achieved because of a large skew between data channels, or because the
stat_rd_dpa_lvds_locked signal becomes deasserted during training, the channel
aligner asserts the err_rd_dpa signal.
8:4 Serializer
The 8:4 serializer block supports an overall deserialization factor of 4 for 64-bit
Stratix GX variations only. It consists of a PLL and a 2:1 multiplexer for each channel.
For more information on using dynamic phase alignment, refer to
and Dynamic Phase
The data processor consists of three sub-blocks.
Control Word Processing & DIP-4
The control word processing and DIP-4 block analyses the control words from the
data stream, and calculates the running DIP-4 value. It detects the following errors:
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SOP8 violations. If SOPs occur less than 8 cycles apart, the err_rd_sop8 signal is
asserted but there is no impact on the received data. In 128- and 64-bit variations,
the clock-domain crossing buffer may fill faster when SOP8 violations occur.
Odd size packet violations. If an odd size packet does not end with the LSB cleared
to zero, the aN_arxerr signal is asserted on EOP. The err_rd_pad_byte_non_zero
signal is also asserted.
EOP aborts. If an EOP abort is received, the aN_arxerr signal is asserted on EOP.
The err_rd_eop_abort signal is also asserted.
DIP-4 errors (refer to
Indication” on page
Reserved control words—data is dropped.
Proper training patterns. The channel aligner block requires proper training
patterns to lock, so if the transmitting device is sending bad training patterns, the
err_rd_tp signal is asserted and the MegaCore function does not lock.
1
Whenever the MegaCore function aborts a packet by asserting the
aN_arxerr signal (as in the odd size packet with LSB not cleared), the
resulting packet is even sized, except in the DIP-4 optimistic mode.
Alignment.
4–18).
“DIP-4 Marking” on page 4–17
POS-PHY Level 4 MegaCore Function User Guide
and
“DIP-4 Out of Service
Appendix F, Static
4–5