IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 26

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

3–4
POS-PHY Level 4 MegaCore Function User Guide
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1
With Individual buffers, the POS-PHY Level 4 MegaCore function provides an
Atlantic first-in first-out (FIFO) buffer for each port. Therefore, there are as many
Atlantic FIFO buffers of the same depth and width—each with a unique Atlantic
interface on the user end—as the number of ports that you select. The individual
buffers supports up to 16 ports.
Timing and routing difficulties may occur when using 16 ports for 128 bit variations;
thus a maximum of 10 ports is recommended for 128-bit variations.
For transmitters for individual buffers variations, a credit-based scheduler is
provided. This scheduler decodes the incoming status channel and decides from
which FIFO buffer (port) to transmit.
The individual buffers for transmitters offer the following advantages:
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For further information on individual buffers for transmitters, refer to
Buffers” on page
For receivers, the individual buffers offer the following advantages:
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For further information on individual buffers for receivers, refer to
Buffers” on page
The SPI-4.2 protocol supports from 1 to 256 ports. When you select the number of
ports, you determine the mode of operation. Single-PHY operation for one port; or
multi-PHY for two to 256 ports. For example, when interfacing to a 10-channel Gbit
Ethernet MAC device the number of ports is 10.
When you use the shared buffer with embedded addressing, the Number of ports
determines the number of port addresses supported by the POS-PHY Level 4 protocol
portion of the MegaCore function, such as the status generator and error checker. Port
addresses 0 to 255 can always be sent and received when using Shared buffer with
embedded addressing.
For the shared buffer with embedded addressing, the Buffer size defines the size of
the shared embedded address buffer. For the individual buffers, the Buffer size
defines the size of each buffer. The POS-PHY Level 4 MegaCore function supports the
following sizes (per buffer):
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A simple user interface
Full scheduler
No head-of-line blocking
Per-port backpressure
A simple user interface
No head-of-line blocking
The POS-PHY Level 4 MegaCore function handles all of the backpressure
automatically
512 bytes
1,024 bytes
5–3.
4–7.
December 2010 Altera Corporation
Chapter 3: Parameter Settings
“Individual
“Individual
Basic Parameters