IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 43

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description—Receiver
Block Description
Figure 4–2. DPA and Channel Aligner Block Diagram
December 2010 Altera Corporation
Serial
DPA Channel Aligner (rx_data_phy_dpa)
Data
f
rdat/rctl
16+1
rdclk
For more information on the ALTLVDS_RX and ALTDDIO_IN megafunctions, refer to
Quartus
Guide, or to the
In the Stratix III, Stratix II, and Stratix GX device families, the ALTLVDS_RX
megafunctions support an optional DPA feature that can compensate for trace length
mismatches and variations due to process, voltage, and temperature (PVT).
The DPA feature includes the following functions:
■
■
■
■
■
■
If the DPA parameter is turned on, the DPA feature consists of an ALTLVDS_RX
megafunction with DPA enabled, and a channel aligner. For 64-bit data path width
variations in Stratix GX devices, this feature also consists of an 8:4 serializer (needed
to achieve an overall deserialization factor of 4). Three status signals:
stat_rd_dpa_locked, err_rd_dpa and stat_rd_dpa_lvds_locked, and one control
signal: ctl_rd_dpa_force_unlock are also part of this feature.
DPA block diagram.
Supports data rates from 415 Mbps to 1 Gbps in Stratix GX devices
Supports data rates from 415 Mbps to 1,250 Gbps in Stratix III devices and to 1,050
Gbps in Stratix II devices
At reset, it performs channel alignment using SPI-4.2 training patterns
compensating for static clock-channel and channel-to-channel skew
After reset, it dynamically follows changing clock-channel and channel-to-channel
skew without using SPI-4.2 training patterns
Supports a total skew of 4.5 bits, with 0.5 bits of the total allowed after reset in
Stratix GX devices
Supports a total skew of 4.4 bits, with 0.4 bits of the total allowed after reset in
Stratix III and Stratix II devices
ALTLVDS_RX
Megafunction
(with DPA)
®
II Help, to the
ALTDDIO Megafunction User
128+/64+
data_out
lvds_reset
16+1
16+1
align
SERDES Transmitter/Receiver ALTLVDS Megafunction User
rx_data_phy_dpa
Channel
Aligner
data_out_algn
128+/64+
Guide.
16+1
Serializer
stat_rd_dpa_lvds_locked (3)
POS-PHY Level 4 MegaCore Function User Guide
x2
PLL
8:4
(2)
ctl_rd_dpa_force_unlock
stat_rd_dpa_locked
128+/64+
data : 2
err_rd_dpa
Figure 4–2
clk x 2
rdint_clk
rxreset_n
Signals
Parallel
Status/
Control
shows the
Data
4–3