IP-POSPHY4 Altera, IP-POSPHY4 Datasheet - Page 73

• Manufacturer Part Number: IP-POSPHY4
• Description: IP CORE - POS-PHY Level 4 SPI 4.2 Interface
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-POSPHY4

• Software Application: IP CORE, Interface And Protocols, COMMUNICATION
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: POS-PHY Level 4 Interface, Link-Layer/PHY Layer
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Features
Block Description
Figure 5–1. Block Diagram—Transmitter
Notes to
(1) The dotted lines illustrate the clock domain separations.
(2) These blocks and signals are only present when the individual buffers mode is selected.
December 2010 Altera Corporation
Figure
5–1:
Interface
SPI4.2
trefclk
tdclk
tsclk
The POS-PHY Level 4 MegaCore
logic, and one of two first-in first-out (FIFO) buffer options: a single shared buffer
with embedded addressing and support for external scheduling, or an individual
buffer for each port including a full scheduler.
When the POS-PHY Level 4 MegaCore function is configured as a transmitter, data
flows from the Atlantic
■
■
■
■
■
Figure 5–1 on page 5–1
MegaCore function.
Sends data packets on the SPI-4.2 interface
Inserts control words
Generates DIP-4
Inserts training sequence
Manages the FIFO buffer status
Parallel-to-Serial
Converter
Status PHY
(Note 1)
Status FSM
Register
5. Functional Description—Transmitter
tdint_clk
Processor
Status
rav_clk
™
shows the blocks and clocks that comprise the transmitter
Data
and
interface to the SPI-4.2 interface.
(2)
®
function consists of the main SPI-4.2 processing
Scheduler
FIFO Buffer
User FIFO
(Note 2)
Scheduler
Buffer
POS-PHY Level 4 MegaCore Function User Guide
(Note 2)
Buffer N
Atlantic
Buffer 0
Atlantic
Atlantic
Interface 0
Atlantic
Interface N
txsys_clk